ADC0852 datasheet(10/20 Pages) NSC

10 / 20 page

Functional Description (Continued)

In actual practice the devices used in the ADC08524 are a

simple but important expansion of the basic comparator de-

scribed above As shown in

Figure 4c multiple differential

comparisons can be made In this circuit the feedback

switch and one input switch on each capacitor (A switches)

are closed in the first cycle Then the other input on each

capacitor is connected while all of the first switches are

opened The change in voltage at the inverter’s input as a

result of the change in charge on each input capacitor (C1

C2) will now depend on both input signal differences

12 Input Sampling and Response Time

The input phases of the comparator relate to the device

clock (CLK) as shown in

Figure 5 Because the comparator

is a sampling device its response characteristics are some-

what different from those of linear comparators The VIN(a)

input is sampled first (CLK high) followed by VIN(b) (CLK

low) The output responds to those inputs one half cycle

later on CLK’s falling edge

The comparator’s response time to an input step is depen-

dent on the step’s phase relation to the CLK signal If an

input step occurs too late to influence the most imminent

comparator decision one more CLK cycle will pass before

the output is correct In effect the response time for the

VIN(a) input has a minimum of 1 CLK cycle a 1 mS and a

maximum of 2 CLK cycles a 1 mS The VIN(b) input’s delay

will range from 12 CLK cycle a 1 mS to 15 CLK cycles a

1 mS since it is sampled after VIN(a)

The sampled inputs also affect the device’s response to

pulsed signals As shown in the shaded areas in

Figure 5

pulses that rise andor fall near the latter part of a CLK half-

cycle may be ignored

13 Input Multiplexer

A unique input multiplexing scheme has been utilized to pro-

vide multiple analog channels with software-configurable

single-ended differential or pseudo-differential operation

The analog signal conditioning required in transducer-input

and other types of data acquisition systems is significantly

simplified with this type of input flexibility One device pack-

age can now handle ground referenced inputs as well as

signals with some arbitrary reference voltage

On the ADC0854 the ‘‘common’’ pin (pin 6) is used as the

‘‘b’’ input for all channels in single-ended mode Since this

input need not be at analog ground it can be used as the

common line for pseudo-differential operation It may be tied

to a reference potential that is common to all inputs and

within the input range of the comparator This feature is

especially useful in single-supply applications where the an-

alog circuitry is biased to a potential other than ground

A particular input configuration is assigned during the MUX

addressing sequence which occurs prior to the start of a

comparison The MUX address selects which of the analog

channels is to be enabled what the input mode will be and

the input channel polarity One limitation is that differential

inputs are restricted to adjacent channel pairs For example

channel 0 and 1 may be selected as a differential pair but

they cannot act differentially with any other channel

The channel and polarity selection is done serially via the DI

input A complete listing of the input configurations and cor-

responding MUX addresses for the ADC0852 and ADC0854

is shown in tables I and II

Figure 6 illustrates the analog

connections for the various input options

The analog input voltage for each channel can range from

50 mV below ground to 50 mV above VCC (typically 5V)

without degrading accuracy

TLH5521 – 13

FIGURE 5 Analog Input Timing

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