LP5562TMXSLASHNOPB datasheet(37/52 Pages) TI1

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LP5562

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SNVS820A – APRIL 2013 – REVISED SEPTEMBER 2015

7.6.13 STATUS/INTERRUPT Register (address = 0Ch) [reset = 00h]

Note:Register INT bits will be cleared when read operation to Status/Interrupt register occurs.

Figure 38. STATUS/INTERRUPT Register

EXT_CLK

ENG1_INT

ENG2_INT

ENG3_INT

USED

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. STATUS/INTERRUPT Register Field Descriptions

Bit

Field

Type

Reset

Description

EXT_CLK USED

External clock state

0 = Internal clock used

1 = External 32kHz clock used

ENG1_INT

Interrupt from engine 1

ENG2_INT

Interrupt from engine 2

ENG3_INT

Interrupt from engine 3

7.6.14 RESET Register (address = 0Dh) [reset = 00h]

Figure 39. RESET Register

RESET[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. RESET Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

RESET

R/W

Reset all register values when FFh is written.

7.6.15 WLED Output PWM Control Register (W_PWM) (address = 0Eh) [reset = 00h]

Figure 40. W_PWM Control Register

W_PWM[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. W_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

W_PWM

R/W

W LED Output PWM value during direct control operation mode

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