18

Integrated JPEG CODEC

decompression), and therefore the transfer can be successfully

completed. A host using this signal must not terminate the RD or

WR strobe before the ZR36060 acknowledges the cycle by

asserting ACK. This can actually stall the host in the middle of a

compressed data stream, or between compressed data fields in

the case of continuous operation, if the host attempts to read (or

write) the FIFO while it is completely empty (or full).

The system must be designed to use CBUSY or ACK output

signal as a handshake, but not both. Maximum code transfer rate

performance is achieved when using CBUSY handshake and

16-bit code bus width.

The host also has access to a status register to interrogate the

full/empty status of the internal code FIFO via the CBUSY bit

(positive logic as opposed to the CBUSY pin state), and to a pair

of read-only bits, CFIFO[1:0], which indicate the fullness of the

code FIFO as follows:

• CFIFO[1:0] == 00b: less than 1/4 of the FIFO is occupied.

• CFIFO[1:0] == 01b: less than 1/2 but more than (or exactly)

1/4 of the FIFO is occupied.

• CFIFO[1:0] == 10b: less than 3/4 but more than (or exactly)

1/2 of the FIFO is occupied.

• CFIFO[1:0] == 11b: more than (or exactly) 3/4 of the FIFO is

occupied.

Using this register, the host can work in a polling method

(instead of using the CBUSY or ACK signals), to determine when

it should momentarily stop the code transfer. However, the

system must guarantee minimum RD and WR strobe widths as

specified in the AC Characteristics.

The CFIFO[1:0] status bits are not valid after the EOI (end of

code stream) signal and status bit has been asserted.

After the last code word is input (in decompression) or output (in

compression), the ZR36060 asserts the EOI signal, indicating

the end of the code stream with the End-Of-Image marker.

5.2.1 Host abort of a code read or write cycle

During the compression or decompression process the host

must obey the handshake rules to create a valid code file. The

host, however, can safely abort (e.g.- due to a timeout) a RD or

WR cycle only after the EOI signal is asserted. If a code transfer

cycle is aborted by the host in the midst of a compression or

decompression process, the behavior of the ZR36060 will be

unpredictable, and the ZR36060 must be reset to resume normal

operation.

Figure 23 shows an example of a code transfer abort after EOI

is asserted.

5.2.2 Data alignment in Code Slave mode

In compression, in code slave mode, the ZR36060 always com-

pletes the compressed data file for each field so that it is 32-bit

(double-word) aligned. This is true for both 8-bit and 16-bit inter-

face modes. A variable number of padding bytes of value 0xFF

are appended by the ZR36060 after the EOI marker, to complete

the last double word. In decompression, such padding bytes

The host reads the status register, receives ACK normally.

The host writes some code bytes (not necessarily two), and the ZR36060 asserts ACK normally. After the second code write

cycle, the ZR36060 senses the end-of-image code indicating the last code byte of the current field and asserts CBUSY .

In this example the host reads a status register, and ACK is granted, independently of CBUSY state.

This is an access to the code FIFO while CBUSY is asserted. No ACK can be issued by the ZR36060, until after the beginning

of the next field. The host is stalled for a while, then decides to abort the cycle, i.e.- release the WR strobe without ACK form

the ZR36060. The ZR36060 senses this situation as an abort of the cycle and ignores the strobe. Again note, that this is only

allowed while EOI is asserted, and not in the middle of the process.

The host now decides to read a status register. This operation is completed normally.

The host writes code into the ZR36060. The ZR36060 has already started decompressing a new field, so CBUSY and EOI are

released and ACK can be issued.

Figure 23. Example of ZR36060 Interleaved Code/Data Accesses and Abort of Access

CS

ADDR[1:0]

RD

Notes:

1.

2, 3.

4.

5.

6.

7.

WR

ACK

CBUSY

EOI

DATA[7:0]

CODE[7:0]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

Data Out

Code In

Code In

Data Out

Try Code In… FAIL!

Data Out

Code In

CFIFO Full

No ACK =

Ignored

11

00

11

00

11

00

1

4

6

2

3

5

7

This example shows status register reads

interleaved with code FIFO write transactions.

After the end-of-image code, instead of waiting

too long (for the ACK signal) until the next field,

the host can decide to abort the cycle.