25

Integrated JPEG CODEC

6.11 Decompression

Before decompression the ZR36060 is in the IDLE state. After

the correct initialization has been done by the host (loading of

parameters and/or tables), the ZR36060 is ready to receive a

command to start decompression. The video bus already

outputs the background color, and if the ZR36060 is a code

slave, CBUSY is asserted, so the host cannot write compressed

data to the ZR36060. The host is now expected to send the start

command. The ZR36060 will then start reading compressed

data (if it is the code bus master), decoding it, and filling up the

strip buffer with pixels. However, pixels will not start flowing out

the video bus before the VSYNC that follows START (or the odd

VSYNC, if FRAME was asserted together with START).

Host controllers that are capable of synchronizing the start

command to VSYNC may do so, providing the start command as

soon as possible after a VSYNC. This makes sure that once

VSYNC arrives, the ZR36060 has enough pixels in the strip

buffer to avoid a condition of strip buffer underflow. In systems

where the video sync signals can be controlled by the host, this

capability can be used to guarantee that START is asserted long

before the next VSYNC.

Once the host controller has sent the start command (by assert-

ing the START signal) CBUSY is deasserted (if it is configured

as output, i.e., in code slave mode), and the RTBSY output is

asserted indicating that the strip memory is initially (close to)

empty (underflow). The host should now provide compressed

data to the ZR36060 as quickly as possible, and fill the strip

memory. Deassertion of RTBSY is an indication that sufficient

data is available in the strip buffer to start video output. Every

time that the ZR36060 senses that the strip buffer is close to an

overflow (full), it asserts an internal flag that stops the transfer of

pixels into the strip buffer, and eventually might result in asser-

tion of CBUSY (in code slave mode) or in stopping of

compressed data acquisition (in code master mode). When the

ZR36060 senses the EOI marker, or when the active portion of

the video field is over (whichever occurs later), it asserts the

END signal and returns to the IDLE state, waiting for a new start

command. (As in compression, the host controller may choose to

leave START asserted continuously, rather than asserting it

after every END).

Figure 37. Examples of ZR36060 Compression (After Host Loaded Parameters & Load Command)

VSYNC

_active

_state

START

FRAME

RTBSY

DATERR

CSS

(code master)

CBUSY

(code slave)

DATA Bus

(CODE bus)

END

JIRQ

1

2

3

4

5

6

7

8

9

10

11

12

ODD

EVEN

ODD

EVEN

ODD

EVEN

ODD

EVEN

ODD

EVEN

ODD

EVEN

IDLE

WaitACT

CMP

i

i

IDLE

CMP

CMP

i

i

CMP

(w/error)

i

CMP

i

WaitISR

CMP

(w/error)

CMP

3

4

5

7

8

10

11

In field #1, START & FRAME asserted indicate to begin on next ODD VSYNC

Wait for next ODD field; meanwhile START signal is ignored (END not asserted)

Field #3 is compressed, active area only, issue END and return to IDLE. At this point, START is sensed low (w/o FRAME) -> start cmp. next

VSYNC (next field).

Field #4 is compressed on active area. Again, after END system assert START w/o FRAME, so next field must be compressed too.

Begin field compression, but system is too slow to take data out to system memory, so DATERR is asserted. Sampling of END and DATERR

inform the system of an illegal field. Since interrupt request on data error is enabled, ZR36060 assert JIRQ and wait until the host

acknowledge the JIRQ by reading the associated interrupt status register.

During this field, the host service the interrupt (ZR36060 de-assert JIRQ) and assert again START (w/o FRAME) for next field compression.

In this example, the host also disables interrupts after servicing this one.

Field #7 is compressed. After END system assert START for next field compression.

Field is compressed normally, but during the last lines of active area, the system response is slow and the last part of the code is fetched at

a much slower pace. Next field #9 begins (VSYNC assertion) without issuing END by the ZR36060. This is an illegal condition indicated by

DATERR. No JIRQ here since interrupts are disabled. START is sensed low for next field compression (ZR36060 skips field #9).

Fields are compressed normally. START is de-asserted during field #11, therefore after END assertion the ZR36060 returns to IDLE and

wait for next operation.

1.

2.

3.

4.

5.

6.

7.

8, 9.

10, 11.

Notes:

i = go through IDLE & WAITACT)