ZR36060PQC datasheet(30/46 Pages) ETC

30 / 46 page

Integrated JPEG CODEC

8.0 REGISTER AND MEMORY DESCRIPTION

The ZR36060 internal memory space is implemented as 1024

bytes of RAM, accessible by the host controller through the host

interface. The contents of this RAM may be loaded into the final

storage registers and tables using the Load command (refer to

6.4 “Loading Parameters and Tables”). Figure 40 depicts the

partitioning of the RAM.

A “default” is specified for each register bit. This is its value after

reset.

8.1 General Control Registers

LOAD Parameters Register

Address 0x000

SyncRst: Resets the video sync generator.

- No reset

- Reset the syncs. Start horizontal/vertical counting from 0, 0. The Sync Gen-

erator is maintained in reset state until the host writes 0 again to this bit.

Load: Load all the internal memory parameters (including tables) to the respective

ZR36060 internal blocks. After writing Load = 1, the ZR36060 sets the Busy bit until

the load is complete and the ZR36060 is ready to operate. The Load bit must be

set every time a new parameter is written anywhere in the internal memory.

- No effect

- Load parameters now

Code FIFO Status Register (Read only)

Address 0x001

CFIFO[1:0]: Indicates the fullness of the Code FIFO (ready only bits):

00 - less than 1/4 of the Code FIFO is occupied.

01 - less than 1/2 but more than (or exactly) 1/4 is occupied.

10 - less than 3/4 but more than (or exactly) 1/2 is occupied.

11 - more than (or exactly) 3/4 of the Code FIFO is occupied.

These bits are valid only when EOI is not asserted.

CBUSY: Indicate the full/empty condition of the code FIFO (read only bit - identical

to CBUSY pin state, inverse logic)

- code FIFO not full / not empty

- code FIFO full / empty

This bit is valid only when CBUSY is an output; i.e.- in code slave mode.

Busy: Status of the Load operation. The internal load of parameters can take

~100 microseconds. The host must poll this bit to know when the ZR36060 is ready

(not Busy) to load a new parameter set or start a compression/decompression

process.

- ZR36060 is ready to operate, no Load operation in progress

- Load is in progress now, don’t access any internal memory location while

this bit is set

Code Interface Register

Address 0x002

CodeMstr: The ZR36060 is the Master or Slave of the Code bus

- Code Slave mode

- Code Master mode

CFIS: Only in Master mode, defines the number of clocks for each code byte

transfer. Must be 0 in Code Slave mode.

- one VCLKx2 cycle

- two VCLKx2 cycles

Endian: Defines the byte ordering when using 16-bit code slave interface. Must be

0 in Master mode or 8-bit Slave mode.

- first byte (‘FF’ of ‘FFD8’ SOI code) is on DATA[7:0] bus

- first byte (‘FF’ of ‘FFD8’ SOI code) is on CODE[7:0] bus

Code16: Defines the code bus width for slave mode only. Must be 0 in Master

mode.

- 8-bit code bus

- 16-bit code bus

Figure 40. Internal Memory Map

000h

022h

030h

052h

060h

3FFh

Codec

Control Registers

Debug (Testing)

Video Registers

Spare

JPEG Markers Array

8 Bits Data

Host Address

Host Data

Host Interface

0x000

Load

SyncRst

type

default

0x001

Busy

CFIFO0

type

default

CBUSY

CFIFO1

0x002

Code16

CodeMstr

type

default

CFIS

–

Endian

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