ADC12DL065

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SNAS249D – MARCH 2005 – REVISED APRIL 2013

Typical Performance Characteristics (continued)

Spectral Response @ 10 MHz Input

Spectral Response @ 32 MHz Input

Figure 33.

Figure 34.

Figure 35.

FUNCTIONAL DESCRIPTION

Operating on a single +3.3V supply, the ADC12DL065 uses a pipeline architecture and has error correction

circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The

user has the choice of using an internal 1.0 Volt or 0.5 Volt stable reference, or using an external reference. Any

external reference is buffered on-chip to ease the task of driving that pin.

The output word rate is the same as the clock frequency, which can be between 15 MSPS and 65 MSPS

(typical) with fully specified performance at 65 MSPS. The analog input for both channels is acquired at the rising

edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. Duty cycle

stabilization and output data format are selectable using the quad state function DF/DCS pin. The output data

can be set for offset binary or two's complement.

A logic high on the power down (PD) pin reduces the converter power consumption to 36 mW.

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