ADC12DL065

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SNAS249D – MARCH 2005 – REVISED APRIL 2013

DIGITAL INPUTS

Digital TTL/CMOS compatible inputs consist of CLK, OEA, OEB, PD, DF/DCS, and MULTIPLEX.

CLK

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range of 15 MHz to 65 MHz with rise and fall times of 2 ns or less. The trace carrying the clock

signal should be as short as possible and should not cross any other signal line, analog or digital, not even at

90°.

The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the

charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This

is what limits the lowest sample rate.

The clock line should be terminated at its source in the characteristic impedance of that line. Take care to

maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905

(SNLA035) for information on setting characteristic impedance.

It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is

used to drive other things, each driven pin should be a.c. terminated with a series RC to ground, as shown in

Figure 38, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor

value is

(6)

impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12DL065 has a Duty Cycle Stabilizer which can be enabled using the DF/DCS pin.

It is designed to maintain performance over a clock duty cycle range of 20% to 80% at 65 MSPS. The Duty Cycle

Stabilizer circuit requires a fast clock edge to produce the internal clock, which is the reason for the rise and fall

time requirement listed in the specifications table.

OEA, OEB

The OEA and OEB pins, when high, put the output pins of their respective converters into a high impedance

state. When either of these pin is low, the corresponding outputs are in the active state. The ADC12DL065 will

continue to convert whether these pins are high or low, but the output can not be read while the pin is high.

Since ADC noise increases with increased output capacitance at the digital output pins, do not use the TRI-

STATE outputs of the ADC12DL065 to drive a bus. Rather, each output pin should be located close to and drive

a single digital input pin. To further reduce ADC noise, a 100

Ω resistor in series with each ADC digital output

pin, located close to their respective pins, should be added to the circuit.

PD

The PD pin, when high, holds the ADC12DL065 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 36 mW with a 65MHz clock and 40mW if the clock is

stopped when PD is high. The output data pins are undefined and the data in the pipeline is corrupted while in

the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and

These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before

conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode,

but can result in a reduction in SNR, SINAD and ENOB performance.

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