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Table 7. Basic Mode Control Register (BMCR), Address 0x00

Bit

Bit Name

Default

Description

Reset

0, RW/SC Reset:

1 = Initiate software Reset / Reset in Process.

0 = Normal operation.

This bit, which is self-clearing, returns a value of one until the reset process is

complete. The configuration is re-strapped.

Loopback

0, RW

Loopback:

1 = Loopback enabled.

0 = Normal operation.

The loopback function enables MII transmit data to be routed to the MII receive

data path.

Setting this bit may cause the descrambler to lose synchronization and produce a

500

µs “dead time” before any valid data will appear at the MII receive outputs.

Speed Selection Strap, RW Speed Select:

When auto-negotiation is disabled writing to this bit allows the port speed to be se-

lected.

1 = 100 Mb/s.

0 = 10 Mb/s.

Auto-Negotiation

Enable

Strap, RW Auto-Negotiation Enable:

Strap controls initial value at reset.

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this

bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex

mode.

Power Down

0, RW

Power Down:

1 = Power down.

0 = Normal operation.

Setting this bit powers down the PHY. Only the register block is enabled during a

power down condition.

Isolate

0, RW

Isolate:

1 = Isolates the Port from the MII with the exception of the serial management.

0 = Normal operation.

Restart Auto-

Negotiation

0, RW/SC Restart Auto-Negotiation:

1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-

Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and

will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-

clear. Operation of the Auto-Negotiation process is not affected by the manage-

ment entity clearing this bit.

0 = Normal operation.

Duplex Mode

Strap, RW Duplex Mode:

When auto-negotiation is disabled writing to this bit allows the port Duplex capa-

bility to be selected.

1 = Full Duplex operation.

0 = Half Duplex operation.

Collision Test

0, RW

Collision Test:

1 = Collision test enabled.

0 = Normal operation.

When set, this bit will cause the COL signal to be asserted in response to the as-

sertion of TX_EN within 512-bit times. The COL signal will be de-asserted within

4-bit times in response to the de-assertion of TX_EN.

6:0

RESERVED

0, RO

RESERVED: Write ignored, read as 0.

DP83847 Datasheet(PDF) 30 Page - National Semiconductor (TI)

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