DP83847 datasheet(41/60 Pages) NSC

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Table 21. PHY Control Register (PHYCTRL), address 0x19

Bit

Bit Name

Default

Description

15:12

Unused

0, RO

PSR_15

0, RW

BIST Sequence select:

1 = PSR15 selected.

0 = PSR9 selected.

BIST_STATUS

0, RO/LL

BIST Test Status:

1 = BIST pass.

0 = BIST fail. Latched, cleared by write to BIST_ START bit.

BIST_START

0, RW

BIST Start:

1 = BIST start.

0 = BIST stop.

BP_STRETCH

0, RW

Bypass LED Stretching:

This will bypass the LED stretching for the Receive, Transmit and

Collision LEDs.

1 = Bypass LED stretching.

0 = Normal operation.

PAUSE_STS

0, RO

Pause Compare Status:

0 = Local Device and the Link Partner are not Pause capable.

1 = Local Device and the Link Partner are both Pause capable.

RESERVED

1, RO/P

Reserved: Must be 1.

LED_CNFG

Strap, RW

This bit is used to bypass the selective inversion on the LED output

for DPLX - this enables its use in non-LED applications.

Mode Description

1 = Led polarity adjusted - DPLX selected.

0 = DPLX active HIGH.

4:0

PHYADDR[4:0]

Strap, RW

PHY Address: PHY address for port.

DP83847 Datasheet(PDF) 41 Page - National Semiconductor (TI)

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