DP83847 datasheet(37/60 Pages) NSC

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5.2 Extended Registers

This register provides a single location within the register set for quick access to commonly accessed information.

Table 16. PHY Status Register (PHYSTS), address 0x10

Bit

Bit Name

Default

Description

15:14

RESERVED

0, RO

RESERVED: Write ignored, read as 0.

Receive Error Latch

0, RO/LH

Receive Error Latch:

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT

(address 0x15, Page 0).

0 = No receive error event has occurred.

Polarity Status

0, RO

Polarity Status:

This bit is a duplication of bit 4 in the 10BTSCR register. This bit will

be cleared upon a read of the 10BTSCR register, but not upon a

read of the PHYSTS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

False Carrier Sense

Latch

0, RO/LH

False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register.

1 = False Carrier event has occurred since last read of FCSCR (ad-

dress 0x14).

0 = No False Carrier event has occurred.

Signal Detect

0, RO/LL

100Base-TX unconditional Signal Detect from PMD.

Descrambler Lock

0, RO/LL

100Base-TX Descrambler Lock from PMD.

Page Received

0, RO

Link Code Word Page Received:

This is a duplicate of the Page Received bit in the ANER register,

but this bit will not be cleared upon a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on

read of the ANER (address 0x06, bit 1).

0 = Link Code Word Page has not been received.

DP83847 Datasheet(PDF) 37 Page - National Semiconductor (TI)

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