DP83847 datasheet(8/60 Pages) NSC

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1.6 Strapping Options/Dual Purpose Pins

A 5 k

Ω resistor should be used for pull-down or pull-up to

change the default strap option. If the default option is

required, then there is no need for external pull-up or pull

down resistors, since the internal pull-up or pull down resis-

tors will set the default value. Please note that the

PHYAD[0:4] pins have no internal pull-ups or pull-downs

and they must be strapped. Since these pins may have

alternate functions after reset is deasserted, they should

not be connected directly to Vcc or GND.

Signal Name

Type

LLP Pin #

Description

LED_DPLX/PHYAD0

LED_COL/PHYAD1

LED_GDLNK/PHYAD2

LED_TX/PHYAD3

LED_RX/PHYAD4

S, O

PHY ADDRESS [4:0]: The DP83847 provides five PHY address

pins, the state of which are latched into the PHYCTRL register at

system Hardware-Reset.

The DP83847 supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). PHY Address 0 puts the part

into the MII Isolate Mode. The MII isolate mode must be selected

by strapping Phy Address 0; changing to Address 0 by register

write will not put the Phy in the MII isolate mode.

The status of these pins are latched into the PHY Control Register

during Hardware-Reset. (Please note these pins have no internal

pull-up or pull-down resistors and they must be strapped high or

low using 5 k

Ω resistors.)

AN_EN

AN_1

AN_0

S, O, PU

Auto-Negotiation Enable: When high enables Auto-Negotiation

with the capability set by ANO and AN1 pins. When low, puts the

part into Forced Mode with the capability set by AN0 and AN1

pins.

AN0 / AN1: These input pins control the forced or advertised op-

erating mode of the DP83847 according to the following table.

The value on these pins is set by connecting the input pins to

GND (0) or VCC (1) through 5 kΩ resistors. These pins should

NEVER be connected directly to GND or VCC.

The value set at this input is latched into the DP83847 at Hard-

ware-Reset.

The float/pull-down status of these pins are latched into the Basic

Mode Control Register and the Auto_Negotiation Advertisement

pins may switch to outputs so if pull-ups or pull-downs are imple-

mented, they should be pulled through a 5 k

Ω resistor.

The default is 111 since these pins have pull-ups.

AN_EN

AN1

AN0

Forced Mode

10BASE-T, Half-Duplex

10BASE-T, Full-Duplex

100BASE-TX, Half-Duplex

100BASE-TX, Full-Duplex

AN_EN

AN1

AN0

Advertised Mode

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

DP83847 Datasheet(PDF) 8 Page - National Semiconductor (TI)

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