Load

Power

Converter

Sense-

TRIM

GND

CSP

CS

Current Sharing

Amplifier

TRO

RSO

R

R

R

R

CS

M

CSO

Remote Sense

Driver

LM5080

SHR

IT

Voltage

Reference

10:

Sense +

Error

Amp

10:

Vou

t

+

Vou

t

-

8R

8R

+VRS -

NRND

LM5080

www.ti.com

SNVS387C – SEPTEMBER 2005 – REVISED MARCH 2013

REFERENCE ADJUSTMENT OPERATION MODE

The reference adjust or trim adjust mode configuration is shown in Figure 13. Typically only the current share

amplifier is used, however the RSO buffer can be optionally configured for boosting the transconductance to

increase the current share loop gain (Figure 14). CSP is left open and CSM is connected to a low side current

sense resistor. The TRO output is connected to the TRIM pin of the power converter to inject a correction that

adjusts the voltage regulator.

To understand the control loop, assume for a moment the SHR pin is disconnected from the share bus. Since

both inputs to the current share amplifier are equal, the TRO output current (IT) is zero and independent of the

sense resistor voltage (VRS). Hence the voltage regulation loop of each converter is unaffected by the LM5080

when the SHR bus is open. When the SHR pins are connected in a 2 supply system, the transfer function

between the sense resistor voltages (VRS1 & VRS2) and the current injected into each power converter TRIM

pin (IT1 & IT2) are as follows:

IT1 = 0.9 x gm x (VRS1 - VRS2)

IT2 = 0.9 x gm x (VRS2 - VRS1)

where

•

gm = current share amplifier transconductance (8.7mA/V)

As long as the current sharing is equal (VRS1=VRS2), the correction to the references (IT1 & IT2) will remain

unchanged. However, any difference between VRS1 and VRS2 will drive the TRIM pin currents in opposite

polarities. As a result the power converter output voltages will be adjusted to force VRS1=VRS2. For 3 or more

channels, the same averaging concept is true; the injected currents (IT) will drive the references such that the

sense voltages are nearly identical.

A capacitor from TRO to ground (CTRO) sets the dominant pole of the current share loop. The pole location is

determined by gm, CTRO and the impedance of the regulator trim pin. The current share loop frequency

response does not need to be fast and in fact should be less than or equal to 1/10th the regulator bandwidth.

Since similar regulators will have similar transient responses to a load step, the LM5080 only needs to correct

the differences in each regulator’s voltage reference and feedback divider which do not require a fast response.

In some systems a small resistor (RTRO) in series with CTRO can improve stability by introducing a zero at high

frequencies to increase the phase margin of the current share loop.

It is essential that the VCC pins of all LM5080’s be tied to the same point in this mode. Any mismatch in the VCC

voltages between LM5080’s will significantly contribute to current share errors. The current sense resistors

should be located as close to the load as possible to minimize trace resistance in series with the sense resistors

which can also contribute to sharing errors. In this mode, the best accuracy will be achieved with lower VCC

values since any mismatch in the gain resistors internal to the LM5080 will affect the current share accuracy.

Figure 13. Reference Adjust Mode Implementation

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