start

msb Chip Address lsb

w

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

ack from slave

ack from slave

SCL

SDA

start

Id = 54h

w

ack

addr = 02h

ack

ack

address 02h data

stop

ADR6

Bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

I

2

C SLAVE address (chip address)

SDA

SCL

S

P

STO

LP3952

www.ti.com

SNVS518A – JULY 2007 – REVISED MARCH 2013

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

addressed must generate an acknowledge after each byte has been received.

eighth bit which is a data direction bit (R/W). The LP3952 address is 54h or 55H as selected with ADDR_SEL

“0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be

written. The third byte contains data to write to the selected register.

Register changes take an effect at the SCL rising edge during the last ACK from slave.

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 7-bit chip address, 54H (ADDR_SEL=0) or 55H (ADDR_SEL=1) for LP3952.

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform.

Copyright © 2007–2013, Texas Instruments Incorporated

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