LP3952RLSLASHNOPB datasheet(33/46 Pages) TI1

33 / 46 page

LP3952

www.ti.com

SNVS518A – JULY 2007 – REVISED MARCH 2013

Table 6. LP3952 Control Register Names and Default Values (continued)

ADDR

(HEX)

cet[1:0]

b[2:0]

tt[2:0]

Command

r[2:0]

g[2:0]

cet[3:2]

Command

cet[1:0]

b[2:0]

tt[2:0]

Command

Reset

Writing any data to Reset Register resets LP3952

LP3952 Registers

Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:

Key

Bit Accessibility

Read/write

Read only

–0,–1

Condition after POR

RGB CTRL (00H) – RGB LEDS CONTROL REGISTER

cc_rgb1

cc_rgb2

r1sw

g1sw

b1sw

r2sw

g2sw

b2sw

rw-1

rw-0

0 - R1, G1 and B1 are constant current sinks, current limited internally

cc_rgb1

Bit 7

1 - R1, G1 and B1 are switches, limit current with external ballast resistor

0 – R2, G2 and B2 are constant current sinks, current limited internally

cc_rgb2

Bit 6

1 – R2, G2 and B2 are switches, limit current with external ballast resistor

0 – R1 disabled

r1sw

Bit 5

1 – R1 enabled

0 – G1 disabled

g1sw

Bit 4

1 – G1 enabled

Bit 3

0 – B1 disabled

b1sw

1 – B1 enabled

0 – R2 disabled

r2sw

Bit 2

1 – R2 enabled

0 – G2 disabled

g2sw

Bit 1

1 – G2 enabled

0 – B2 disabled

b2sw

Bit 0

1 – B2 enabled

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