LP3952RLSLASHNOPB datasheet(4/46 Pages) TI1

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LP3952

SNVS518A – JULY 2007 – REVISED MARCH 2013

www.ti.com

Operating Ratings

(1) (2) (continued)

VDDIO

1.65V to VDD1

Voltage on ASE

0.1V to VDDA –0.1V

Recommended Load Current

0 to 300 mA

Junction Temperature (TJ) Range

-30°C to +125°C

Ambient Temperature (TA) Range

(3)

-30°C to +85°C

(3)

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (

θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).

Thermal Properties

Junction-to-Ambient Thermal Resistance(

θJA), YPG0036AAA Package

(1)

60°C/W

(1)

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

Electrical Characteristics

(1) (2)

Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the operating ambient temperature range (-

30°C < TA < +85°C). Unless otherwise noted, specifications apply to the LP3952 Block Diagram with: VDD1 = VDD2 = 3.6V,

VDDIO = 2.8V, CVDD = CVDDIO = 100 nF, COUT = CIN = 10 μF, CVDDA = 1 μF, CREF = 100 nF, L1 = 4.7 μH, RRGB = 5.6 kΩ and RRT

= 82 k

(3).

Parameter

Test Conditions

Min

Typ

Max

Units

IVDD

Standby supply current

NSTBY (bit) = L, NRST (pin) = H

μA

(VDD1 + VDD2)

SCL=H, SDA = H

No-boost supply current

NSTBY (bit) = H,

450

μA

(VDD1 + VDD2)

EN_BOOST(bit) = L

SCL = H, SDA = H

Audio sync and LEDs OFF

No-load supply current

NSTBY (bit) = H,

(VDD1 + VDD2)

EN_BOOST (bit) = H

SCL = H, SDA = H

Audio sync and LEDs OFF

Autoload OFF

RGB drivers

CC mode at R1, G1, B1 and R2, G2, B2 set to 15 mA

150

μA

(VDD1 + VDD2)

SW mode

150

IVDD

Audio synchronization

Audio sync ON

(VDD1 + VDD2)

VDD1,2 = 2.8V

390

μA

VDD1,2 = 3.6V

700

IVDDIO

VDDIO Standby Supply

NSTBY (bit)=L

μA

current

SCL = H, SDA = H

IEXT_LDO

External LDO output

7V tolerant application only

6.5

current

IBOOST = 300 mA

(VDD1, VDD2, VDDA)

VDDA

Output voltage of internal

(4)

2.72

2.80

2.88

LDO for analog parts

-3

(1)

All voltages are with respect to the potential at the GND pins.

(2)

Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the

most likely norm.

(3)

Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4)

VDDA output is not recommended for external use.

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