MCP3906AT-ISLASHSS datasheet(16/32 Pages) MICROCHIP

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MCP3905A/05L/06A

DS22011B-page 16

4.1

Analog Inputs

The

MCP3905A/05L/06A

analog

inputs

can

connected

directly

the

current

and

voltage

transducers (such as shunts or current transformers).

Each input pin is protected by specialized ESD

structures that are certified to pass 5 kV HBM and

500V MM contact charge. These structures also allow

up to ±6V continuous voltage to be present at their

inputs without the risk of permanent damage.

Both channels have fully differential voltage inputs for

better noise performance. The absolute voltage at each

pin relative to AGND should be maintained in the ±1V

range during operation in order to ensure the

measurement error performance. The common-mode

signals should be adapted to respect both the previous

conditions and the differential input voltage range. For

best performance, the common-mode signals should

be referenced to AGND.

The current channel comprises a PGA on the front-end

to allow for smaller signals to be measured without

additional signal conditioning. The maximum differen-

tial voltage specified on Channel 0 is equal to

±470 mV/Gain (see Table 4-1). The maximum peak

voltage specified on Channel 1 is equal to ±660 mV.

4.2

16-Bit Delta-Sigma A/D Converters

The ADCs used in the MCP3905A/05L/06A for both

current and voltage channel measurements are delta-

sigma ADCs. They comprise a second-order, delta-

sigma modulator using a multi-bit DAC and a third-

order SINC filter. The delta-sigma architecture is very

appropriate for the applications targeted by the

MCP3905A/05L/06A because it is a waveform-oriented

converter architecture that can offer both high linearity

and low distortion performance throughout a wide input

dynamic range. It also creates minimal requirements

for

the

anti-aliasing

filter

design.

The

multi-bit

architecture used in the ADC minimizes quantization

noise at the output of the converters without disturbing

the linearity.

Both ADCs have a 16-bit resolution, allowing wide input

dynamic range sensing. The oversampling ratio of both

converters is 64. Both converters are continuously

converting during normal operation. When the MCLR

pin is low, both converters will be in Reset and output

code 0x0000h. If the voltage at the inputs of the ADC is

larger than the specified range, the linearity is no longer

specified. However, the converters will continue to

produce output codes until their saturation point is

reached. The DC saturation point is around 700 mV for

Channel 0 and 1V for Channel 1, using internal voltage

reference.

The clocking signals for the ADCs are equally

distributed between the two channels in order to

minimize phase delays to less than 1 MCLK period

(see Section 3.2 “High-Pass Filter Input Logic Pin

(HPF)”). The SINC filter’s main notch is positioned at

MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing

the user to be able to measure wide harmonic content

on either channel. The magnitude response of the

SINC filter is shown in Figure 4-2.

FIGURE 4-2:

SINC Filter Magnitude

Response (MCLK = 3.58 MHz).

TABLE 4-1:

MCP3905A/MCP3905L GAIN

SELECTIONS

CH0 Gain

Maximum

CH0 Voltage

1±470 mV

2±235 mV

8±60 mV

±30 mV

TABLE 4-2:

MCP3906A GAIN

SELECTIONS

CH0 Gain

Maximum

CH0 Voltage

1±470 mV

±15 mV

8±60 mV

±30 mV

-120

-100

-80

-60

-40

-20

Frequency (kHz)

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