CS89712 datasheet(78/170 Pages) CIRRUS

78 / 170 page

CS89712

DS502PP2

Notes: 1. All registers are accessed as 16-bit only.

2. Read operation from the reserved location provides undefined data. Writing to a reserved location or

undefined bits may result in unpredictable operation.

3.4 I/O Port Data Registers

3.4.1

PADR Port A Data Register (address 0x8000.0000)

Values written to this 8-bit read / write register will be output on Port A pins if the corresponding data direc-

tion bits are set high (port output). Values read from this register reflect the external state of Port A, not nec-

essarily the value written to it. All bits are cleared by a system reset.

3.4.2

PBDR Port B Data Register (address 0x8000.0001)

Values written to this 8-bit read / write register will be output on Port B pins if the corresponding data direc-

tion bits are set high (port output). Values read from this register reflect the external state of Port B, not nec-

essarily the value written to it. All bits are cleared by a system reset.

0138

Bus Status

0140h

Reserved

Note 2

Initiate Transmit Registers

0144h

TxCMD (transmit

command)

Section 3.19,

“Initiate Transmit Registers”,

Section 2.34,

“Transmit Operation”

0146h

TxLength (transmit length)

Section 3.19,

“Initiate Transmit Registers”,

Section 2.34,

“Transmit Operation”

0148h

Reserved

Note 2

Address Filter Registers

0150h

Logical Address Filter

(hash table)

Section 3.20,

“Address Filter Registers”,

Section 2.32.7,

“Receive Ethernet Port

Locations”

0158h

Individual Address

Section 3.20,

“Address Filter Registers”,

Section 2.32.7,

“Receive Ethernet Port

Locations”

015Eh

674

Reserved

Note 2

Frame Location

0400h

RXStatus (receive status)

Section 3.18,

“Ethernet Port Status/Control

Registers”,

Section 2.32,

“Basic Receive Operation”

0402h

Read-only RxLength (receive length,

in bytes)

Section 3.18,

“Ethernet Port Status/Control

Registers”,

Section 2.32,

“Basic Receive Operation”

0404h

Read-only Receive Frame Location

Section 3.18,

“Ethernet Port Status/Control

Registers”,

Section 2.32,

“Basic Receive Operation”

0A00

Write-only Transmit Frame Location

Section 3.18,

“Ethernet Port Status/Control

Registers”,

Section 2.34,

“Transmit Operation”

Internal

Offset

# of

Bytes

Type

Description

Cross Reference

Table 36. Ethernet Port 4 Kbyte Memory Register Address Map (Continued)

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