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CS89712 Datasheet(PDF) 1 Page - Cirrus Logic |
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CS89712 Datasheet(HTML) 1 Page - Cirrus Logic |
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1 / 170 page  Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. 1 Copyright © Cirrus Logic, Inc. 2001 (All Rights Reserved) P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com CS89712 High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller Features l ARM720T (ARM7 TDMI) processor – 8 Kbytes of four-way set-associative cache – MMU with 64-entry TLB – Write Buffer – Thumb code support enabled l Dynamically clocked at 18, 36, 49 or 74 MHz l 10 Mbit Ethernet Controller with integrated PHY l Comprehensive Suite of Software Drivers l On-Chip Transmit and Receive RAM Buffers l 10BASE-T Port with Analog Filters provides automatic polarity detection and correction l Programmable Transmit Features: – Automatic Re-transmission on Collision – Automatic Padding and CRC Generation l Programmable Receive Features: – Early Interrupts for Frame Pre-Processing – Automatic Rejection of Erroneous Packets Description The low-power high-performance CS89712 is designed for ultra-low-power communication applications such as VoIP telephones, industrial control, data acquisition, special purpose servers and RF to Ethernet bridges. The core-logic functionality of the device is built around an ARM720T processor with 8 Kbytes of four-way set-asso- ciative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operat- ing systems like embedded Linux. The CS89712 Ethernet port includes on-chip RAM and 10BASE-T transmit and receive filters. ORDERING INFO CS89712-CB 0 to 70° C 256 Ball PBGA 17x17 mm 32.768-KHZ OSCILLATOR PLL INTERRUPT CONTROLLER POWER MANAGEMENT SSI1 (ADC) LCD CONTROLLER ARM7TD 8-KBYTE CACHE MMU TIMER CODE ARM720T INTERNAL DATA BUS PWM 3.6864 MHZ 32.768 KHZ EINT[1-2], FIQ, MEDCHG BATOK, EXPWR PWRFL, BATCHG PORTS A, B, D (8-BIT) PORT E (3-BIT) KEYBD DRIVERS (0–7) BUZZER DRIVE SSI (ADC) INTERFACE DAI / SSI / ADC INTERFACE UART IrDA D[0-31] NPOR, RUN, RESET, WAKEUP EXPCLK, WORD, NCS[0:3], EXPRDY, WRITE A[0-27], DRA[0-14] LCD DRIVE LED AND PHOTODIODE ASYNC INTERFACE 2 GPIO INTERNAL ADDRESS BUS ON-CHIP BOOT ROM ASYNC INTERFACE 1 ON-CHIP SRAM 48K BYTES CL-PS6700 INTFCE. PB[0:1], NCS[4:5] EXPANSION CONTROL UART SSI2 EPB EPB BUS RTC FLASHING LED DRIVE ICE-JTAG TEST AND DEVELOPMENT WRITE BUFFER DAI STATE CNTRL MEMORY CONTROLLER LCD DC-TO-DC SDRAM CNTRL MOE, MWE, SDCLK, SDQM[0:1], SDRAS, SDCAS 10BASE-T ETHERNET FEB ‘01 DS502PP2 |
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