CS89712 datasheet(39/170 Pages) CIRRUS

39 / 170 page

CS89712

DS502PP2

Both directions, however, have an absolute maxi-

mum data throughput rate determined by the maxi-

mum possible clock frequency, assuming that the

interrupt response of the target OS is quick enough.

2.17.4.3

Continuous Data Transfer

Data bytes may be sent/received in a contiguous

manner without interleaving clocks between bytes.

The frame sync control line(s) are eight clocks

apart and aligned with the clock representing bit D0

of the preceding byte (i.e. one bit before the MSB).

2.17.4.4

Discontinuous Clock

In order to save power during the idle times, the

clock line is put into a static low state. The master

is responsible for putting the link into the Idle State.

The Idle State will begin one clock, or more, after

the last byte transferred and will resume at least one

clock prior to the first frame sync assertion. To dis-

able the clock, the TX section is turned off.

In Master mode, the CS89712 does not support the

discontinuous clock.

2.17.4.5

Error Conditions

RX FIFO overflows are detected and conveyed via

a status bit in the SYSFLG2 register. This register

should be accessed at periodic intervals by the ap-

plication software. The status register should be

read each time the RX FIFO interrupts are generat-

ed. At this time the error condition (i.e., overrun

flag) will indicate that an error has occurred but

cannot convey which byte contains the error. Writ-

ing to the SRXEOF register location clears the

overrun flag. TX FIFO underflow condition is de-

tected and conveyed via a bit in the SYSFLG2 reg-

ister, which is accessed by the application software.

A TX underflow error is cleared by writing data to

be transmitted to the TX FIFO.

2.17.4.6

Clock Polarity

Clock polarity is fixed. TX data is presented on the

bus on the rising edge of the clock. Data is latched

into the receiving device on the falling edge of the

clock. The TX pin is held in a tristate condition

when not transmitting.

2.18 LCD Controller

The LCD controller provides all the necessary con-

trol signals to interface directly to a single panel

multiplexed LCD.

The panel size is programmable and can be any

width (line length) from 32 to 1024 pixels in 16-

pixel increments. The total video frame buffer size

is programmable up to 128 kbytes. This equates to

a theoretical maximum panel size of 1024 x

256 pixels in 4 bits-per-pixel mode. The video

frame buffer can be located in any portion of mem-

ory controlled by the chip selects. Its start address

will be fixed at address 0x0000.0000 within each

chip select. The start address of the LCD video

frame buffer is defined in the FBADDR[3:0] regis-

ter. These bits become the most significant nibble

of the external address bus. The default start ad-

dress is 0xC000.0000 (FBADDR = 0xC).

A system built using the on-chip SRAM (OCSR),

will then serve as the LCD video frame buffer and

miscellaneous data store. The LCD video frame

buffer start address should be set to 0x6 in this op-

tion. Programming of the register FBADDR is only

permitted when the LCD is disabled (this is to

avoid possible cycle corruption when changing the

progress). There is no hardware protection to pre-

vent this. It is necessary to disable the LCD control-

ler before reprogramming the FBADDR register.

Full address decoding is provided for the OCSR, up

to the maximum video frame buffer size program-

mable into the LCDCON register. Beyond this, the

address is wrapped around. The frame buffer start

address must not be programmed to 0x4 or 0x5 if

either CL-PS6700 interface is in use (PCMEN1 or

PCMEN2 bits in the SYSCON2 register are en-

abled). FBADDR should never be programmed to

CS89712 Datasheet(PDF) 39 Page - Cirrus Logic

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