CS89712 datasheet(37/170 Pages) CIRRUS

37 / 170 page

CS89712

DS502PP2

data rate, the required interrupt rate will be greater

than 1 msec, which is acceptable.

There are separate half-word-wide RX and TX

FIFOs (16 half-words each) and corresponding in-

terrupts which are generated when the FIFO’s are

half-full or half-empty as appropriate. The inter-

rupts are called SS2RX and SS2TX, respectively.

There are five pins to support this SSI port: SSIRX-

DA, SSITXFR, SSICLK, SSITXDA, and SSIRX-

FR. The SSICLK, SSIRXDA, SSIRXFR, and

SSITXFR signals are inputs and the SSITXDA sig-

nal is an output in slave mode. In the master mode,

SSICLK, SSITXDA, SSITXFR, and SSIRXFR are

outputs, and SSIRXDA is an input. Master mode is

enabled by writing a one to the SS2MAEN bit

(SYSCON2[9]). When the master / slave SSI is not

required, it can be disabled to save power by writ-

ing a zero to the SS2TXEN and the SS2RXEN bits

(SYSCON2[4] [7]). When set, these two bits inde-

pendently enable the transmit and receive sides of

the interface. The master/slave SSI is synchronous,

full duplex, and capable of supporting serial data

transfers between two nodes. Although the inter-

face is byte-oriented, data is loaded in blocks of

two bytes at a time. Each data byte to be transferred

is marked by a frame sync pulse, lasting one clock

period, and located one clock prior to the first bit

being transferred. Direction of the SSI2 ports, in

slave and master mode, is shown in Figure 9.

Data on the link is sent MSB first and coincides

with an appropriate frame sync pulse, one clock in

duration, located one clock prior to the first data bit

(MSB). It is not possible to send data LSB first.

When operating in master mode, the clock frequen-

cy is selected to be the same as the ADC interface’s

(master mode only SSI1) — that is, the frequencies

are selected by the same bits 16 and 17 of the

SYSCON1 register (i.e., the ADCKSEL bits).

Thus, the maximum frequency in master mode is

128 kbits/s. The interface will support continuous

transmission at this rate assuming that the OS can

respond to the interrupts within 1 msec to prevent

over/underruns.

Note:

To allow synchronization to the incoming slave

clock, the interface enable bits will not take

effect until one SSICLK cycle after they are

written and the value read back from

SYSCON2. The enable bits reflect the real

status of the enables internally. Hence, there

will be a delay before the new value

programmed to the enable bits can be read

back.

The timing diagram for this interface can be found

in Section 6.3.

Figure 9. SSI2 Port Directions in Slave and Master Mode

Slave 7211

SSIRXFR

SSITXFR

SSICLK

SSIRXDA

SSITXDA

Master 7211

SSIRXFR

SSITXFR

SSICLK

SSITXDA

SSIRXDA

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