MCP73871-2CCISLASHML datasheet(28/40 Pages) MICROCHIP

28 / 40 page

MCP73871

DS20002090C-page 28

 2008-2013 Microchip Technology Inc.

6.1

Application Circuit Design

Due to the low efficiency of linear charging, the most

important factors are thermal design and cost, which

are a direct function of the input voltage, output current

and thermal impedance between the battery charger

and the ambient cooling air. The worst-case situation is

when

the

device

has

transitioned

from

the

Preconditioning mode to the Constant Current mode. In

this situation, the battery charger has to dissipate the

maximum power. A trade-off must be made between

the charge current, cost and thermal requirements of

the charger.

6.1.1

COMPONENT SELECTION

Selection of the external components in Figure 6-1 is

crucial to the integrity and reliability of the charging

system. The following discussion is intended as a guide

for the component selection process.

6.1.1.1

Charge Current

The preferred fast charge current for Lithium-Ion cells

should always follow references and guidances from

battery manufacturers. For example, a 1000 mAh

battery pack has a preferred fast charge current of

0.7C. Charging at 700 mA provides the shortest charge

cycle times without degradation to the battery pack

performance or life.

6.1.1.2

Thermal Considerations

The worst-case power dissipation in the battery

charger occurs when the input voltage is at the

maximum and the device has transitioned from the

Preconditioning mode to the Constant Current mode. In

this case, the power dissipation is:

EQUATION 6-1:

For example, power dissipation with a 5V, ±10% input

voltage source and 500 mA, ±10% fast charge current

is:

EXAMPLE 6-1:

This power dissipation with the battery charger in the

QFN-20 package causes thermal regulation to enter as

depicted. Alternatively, the 4 mm x 4 mm DFN package

could be utilized to reduce heat by adding vias on the

exposed pad.

6.1.1.3

External Capacitors

The MCP73871 device is stable with or without a

battery load. To maintain good AC stability in the Con-

stant Voltage mode, a minimum capacitance of 4.7 μF

is recommended to bypass the VBAT pin to VSS. This

capacitance provides compensation when there is no

battery

load.

addition,

the

battery

and

interconnections appear inductive at high frequencies.

These elements are in the control feedback loop during

Constant Voltage mode. Therefore, the bypass

capacitance may be necessary to compensate for the

inductive nature of the battery pack.

Virtually any good quality output filter capacitor can be

used, regardless of the capacitor’s minimum Effective

Series Resistance (ESR) value. The actual value of the

capacitor (and its associated ESR) depends on the

output load current. A 4.7 μF ceramic, tantalum or

aluminum electrolytic capacitor at the output is usually

sufficient to ensure stability for charge currents up to

1000 mA.

6.1.1.4

Reverse-Blocking Protection

The MCP73871 device provides protection from a

faulted or shorted input. Without the protection, a

faulted or shorted input would discharge the battery

pack through the body diode of the internal pass

transistor.

6.1.1.5

Temperature Monitoring

The charge temperature window can be set by placing

fixed value resistors in series-parallel with a thermistor.

The resistance values of RT1 and RT2 can be calculated

with the following equations to set the temperature win-

dow of interest.

For NTC thermistors:

EQUATION 6-2:

PowerDissipation

V DDMAX V PTHMIN

–

 I

REGMAX



Where:

VDDMAX = the maximum input voltage

IREGMAX = the maximum fast charge current

VPTHMIN = the minimum transition threshold

voltage

PowerDissipation

5.5V

2.7V

–

 550mA



1.54W

24k



RT1

RT2 RCOLD



RT2 R

COLD

----------------------------------



RT1

RT2 RHOT



RT2 R

HOT

-------------------------------

Where:

RT1

the fixed series resistance

RT2

the fixed parallel resistance

RCOLD

the thermistor resistance at the

lower temperature of interest

RHOT

the thermistor resistance at the

upper temperature of interest

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