MCP73871-2CCISLASHML datasheet(17/40 Pages) MICROCHIP

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DS20002090C-page 17

MCP73871

3.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

3.1

Power Supply Input (IN)

supply

voltage

VREG + 0.3V to 6V is

recommended. Bypass to VSS with a minimum of

4.7 μF.

3.2

System Output Terminal (OUT)

The MCP73871 device powers the system via output

terminals while independently charging the battery.

This feature reduces the charge and discharge cycles

on the battery, allowing proper charge termination and

the system to run with an absent or defective battery

pack. It also gives the system priority on input power,

allowing the system to power up with deeply depleted

battery packs. Bypass to VSS with a minimum of 4.7 μF

is recommended.

3.3

Voltage Proportional Charge

Control (VPCC)

If the voltage on the IN pin drops to a preset value,

determined by the threshold established at the VPCC

input, due to a limited amount of input current or input

source impedance, the battery charging current is

reduced. If possible, further demand from the system is

supported by the battery. To enable this feature, simply

supply 1.23V or greater to the VPCC pin. This feature

can be disabled by connecting the VPCC pin to IN.

For example, a system is designed with a 5.5V rated

DC power supply with ±0.5V tolerance. The worst

condition of 5V is selected, which is used to calculate

the VPCC supply voltage with divider.

TABLE 3-1:

PIN FUNCTION TABLE

Number

Symbol

I/O

Function

1, 20

OUT

System Output Terminal

VPCC

Voltage proportional charge control

SEL

Input type selection (Low for USB port, High for AC-DC adapter)

PROG2

USB port input current limit selection when SEL = Low

(Low = 100 mA, High = 500 mA)

THERM

I/O

Thermistor monitoring input and bias current

Power-Good Status Output (Open-Drain)

STAT2

Charge Status Output 2 (Open-Drain)

STAT1/LBO

Charge Status Output 1 (Open-Drain). Low battery output indicator when

VBAT > VIN

Timer Enable; Enables Safety Timer when active Low

10, 11, EP

VSS

—

Battery Management 0V Reference. EP (Exposed Thermal Pad).

There is an internal electrical connection between the exposed thermal pad and

VSS. The EP must be connected to the same potential as the VSS pin on the

Printed Circuit Board (PCB)

PROG3

I/O

Termination set point for both AC-DC adapter and USB port

PROG1

I/O

Fast charge current regulation setting with SEL = High. Preconditioning set point

for both USB port and AC-DC adapter

14, 15

VBAT

I/O

Battery Positive Input and Output connection

VBAT_SENSE

I/O

Battery Voltage Sense

Device Charge Enable; Enabled when CE = High

18, 19

Power Supply Input

Legend: I = Input, O = Output, I/O = Input/Output

Note:

To ensure proper operation, the input pins must not allow floating and should always tie to either High or

Low.

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