NECVR4102 datasheet(39/420 Pages) EPSON

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Epson Research and Development

Page 31

Vancouver Design Center

Hardware Functional Specification

SED1374

Issue Date: 99/04/29

X26A-A-001-02

7.1.4 Motorola M68K #2 Interface Timing

Figure 7-4: M68K #2 Timing (MC68030)

Note

CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off

BCLK Between Accesses” on page 86

Table 7-4: M68K #2 Timing (MC68030)

Symbol

Parameter

Min

Max

Units

fCLK

Bus Clock frequency

MHz

TCLK

Bus Clock period

1/fCLK

A[15:0], CS#, SIZ0, SIZ1 valid before AS# falling edge

A[15:0], CS#, SIZ0, SIZ1 hold from AS#, DS# rising edge

AS# low to DSACK1# driven high

CLK to DSACK1# low

AS# high to DSACK1# high

AS# high to DSACK1# high impedance

TCLK

DS# falling edge to D[31:16] valid (write cycle)

TCLK / 2

AS#, DS# rising edge to D[31:16] invalid (write cycle)

D[31:16] valid to DSACK1# low (read cycle)

t10

AS#, DS# rising edge to D[31:16] high impedance

A[15:0]

AS#

DS#

VALID

R/W#

Hi-Z

CS#

SIZ0, SIZ1

CLK

DSACK1#

Hi-Z

TCLK

VALID

Hi-Z

D[31:16]

VALID

Hi-Z

t10

(write)

(read)

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