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NECVR4102 Datasheet(PDF) 49 Page - Epson Company |
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NECVR4102 Datasheet(HTML) 49 Page - Epson Company |
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49 / 420 page  Epson Research and Development Page 41 Vancouver Design Center Hardware Functional Specification SED1374 Issue Date: 99/04/29 X26A-A-001-02 7.3.5 Single Color 4-Bit Panel Timing Figure 7-14: Single Color 4-Bit Panel Timing VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8Ts HNDP = Horizontal Non-Display Period = (REG[08h] + 4) x 8Ts VDP FPLINE FPDAT[7:4] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 FPFRAME LINE1 LINE2 FPLINE DRDY (MOD) FPDAT6 FPDAT5 FPDAT4 FPDAT7 DRDY (MOD) VNDP 1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3 1-B3 1-R4 1-G4 1-B4 1-B319 1-R320 1-G320 1-B320 HDP HNDP * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel FPSHIFT |
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