NECVR4102 datasheet(46/420 Pages) EPSON

46 / 420 page

Page 38

Epson Research and Development

Vancouver Design Center

SED1374

Hardware Functional Specification

X26A-A-001-02

Issue Date: 99/04/29

Figure 7-11: Single Monochrome 4-Bit Panel A.C. Timing

= pixel clock period

t1min

= t3min - 9Ts

t3min

= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts

t6min

= [(REG[08h] bits 4-0) x 8 + 2]Ts

t7min

= [(REG[08h] bits 4-0) x 8 + 11]Ts

Symbol

Parameter

Min

Typ

Max

Units

Frame Pulse setup to Line Pulse falling edge

note 2

(note 1)

Frame Pulse hold from Line Pulse falling edge

Line Pulse period

note 3

Line Pulse pulse width

MOD delay from Line Pulse rising edge

Shift Pulse falling edge to Line Pulse rising edge

note 4

Shift Pulse falling edge to Line Pulse falling edge

note 5

Line Pulse falling edge to Shift Pulse falling edge

t14 + 2

Shift Pulse period

t10

Shift Pulse pulse width low

t11

Shift Pulse pulse width high

t12

FPDAT[7:4] setup to Shift Pulse falling edge

t13

FPDAT[7:4] hold to Shift Pulse falling edge

t14

Line Pulse falling edge to Shift Pulse rising edge

Frame Pulse

Line Pulse

DRDY (MOD)

Sync Timing

Line Pulse

Shift Pulse

FPDAT[7:4]

Data Timing

t12

t13

t14

t10

t11

Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

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