STS1TX datasheet(60/70 Pages) STMICROELECTRONICS

60 / 70 page

STS1TX

60/70

DocID025109 Rev 1

PA_POWER[0]

0x18

7:6

CWC[1:0]

R/W

Output stage additional load

capacitors bank (to be used to

optimize the PA for different

sub-bands):

00: 0 pF

01: 1.2 pF

10: 2.4 pF

11: 3.6 pF

PA_RAMP_ENABLE

1: enable the power ramping

4:3

PA_RAMP_STEP_W

IDTH[1:0]

Step width (unit: 1/8 of bit

period)

2:0

PA_LEVEL_MAX_IN

DEX

111

Final level for power ramping or

selected output power index.

Table 35. Radio configuration registers (analog blocks) (continued)

Address

Bit

Field Name

Reset

R/W

Description

Table 36. Radio configuration registers (digital blocks)

Address

Bit

Field Name

Reset

R/W

Description

MOD1

0x1A

7:0

DATARATE_M

0x83

R/W

The mantissa value of the data

rate equation (see Equation 8)

MOD0

0x1B

7CW

R/W

1: enable the CW transmit

mode

BT_SEL

Select BT value for GFSK

0: BT = 1

1: BT = 0.5

5:4

MOD_TYPE[1:0]

Modulation type

0: 2-FSK

1: GFSK

2: ASK/OOK

3: MSK

3:0

DATARATE_E

1010

The exponent value of the data

rate equation (see Equation 8)

FDEV0

0x1C

7:4

FDEV_E[3:0]

0100

R/W

The exponent value of the

frequency deviation equation

(see Equation 7)

CLOCK_REC_ALGO

_SEL

Select PLL or DLL mode for

symbol timing recovery

2:0

FDEV_M

101

The mantissa value of the

frequency deviation equation

(see Equation 7)

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