PC87570 datasheet(5/168 Pages) NSC

5 / 168 page

Table of Contents

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3.2.3

Byte Accessing ............................................................................................................ 34

3.3

CLOCK AND BUS CYCLES ...................................................................................................... 34

3.3.1

Clock Cycles ................................................................................................................ 34

3.3.2

Control Signals ............................................................................................................ 35

3.3.3

Early Write Bus Cycle .................................................................................................. 36

3.3.4

Late Write Bus Cycle ................................................................................................... 38

3.3.5

Normal Read Bus Cycle .............................................................................................. 40

3.3.6

Fast Read Bus Cycle ................................................................................................... 42

3.3.7

I/O Expansion Bus Cycles ........................................................................................... 43

3.3.8

I/O Expansion Example ............................................................................................... 44

3.4

DEVELOPMENT SUPPORT ..................................................................................................... 44

3.4.1

Bus Status Signals ...................................................................................................... 44

3.4.2

Core Bus Monitoring .................................................................................................... 44

3.5

BIU REGISTERS ....................................................................................................................... 45

3.5.1

BIU Configuration Register (BCFG) ............................................................................ 45

3.5.2

I/O Zone Configuration Register (IOCFG) ................................................................... 45

3.5.3

Static Zone Configuration Register (SZCFGn) ............................................................ 45

3.6

USAGE HINTS .......................................................................................................................... 46

4.0

On-Chip Memory

4.1

INTERNAL RAM ........................................................................................................................ 47

4.2

INTERNAL ROM ........................................................................................................................ 47

4.2.1

Access Times .............................................................................................................. 47

4.2.2

ROM Shadow .............................................................................................................. 47

5.0

Host Bus Interface (HBI)

5.1

FEATURES ................................................................................................................................ 48

5.2

HOST ACCESS TO SHARED MEMORY DEVICE ................................................................... 49

5.2.1

Enabling Shared Memory Mode .................................................................................. 49

5.2.2

Memory Device Interface ............................................................................................. 49

5.2.3

Host Access to Shared Memory .................................................................................. 49

5.3

CORE ACCESS TO RTC/APC .................................................................................................. 49

5.3.1

Host and CR16A Arbitration over RTC/APC ............................................................... 49

5.4

USAGE HINTS .......................................................................................................................... 49

5.4.1

Shared Memory ........................................................................................................... 49

5.4.2

Wake-Up from Host ..................................................................................................... 50

5.4.3

Host Power-on Indication ............................................................................................ 50

5.5

HOST ACCESS TO PC87570 RESIDENT I/O DEVICES ......................................................... 50

5.5.1

Host Access to Configuration Registers ...................................................................... 50

5.5.2

Host Access to Resident I/O Devices .......................................................................... 50

5.5.3

Host Bus I/O Cycles .................................................................................................... 50

5.6

KBC CHANNEL ......................................................................................................................... 50

5.6.1

Status Register ............................................................................................................50

5.6.2

DBBOUT Register ....................................................................................................... 51

5.6.3

DBBIN Register ........................................................................................................... 51

PC87570 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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