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ST72325xxx-Auto

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Doc ID 13770 Rev 3

19.8

I/O port pin characteristics

19.8.1

General characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Table 128.

I/O port pin general characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage(1)

CMOS ports

0.3xVDD

VIH

Input high level voltage(1)

0.7xVDD

Vhys

Schmitt trigger voltage hysteresis(2)

0.7

IINJ(PIN)

(3)

Injected current on PB0 pin

VDD =5V

0+4

Injected current on an I/O pin

±4

I

INJ(PIN)

(3) Total injected current (sum of all I/O and

control pins)

±25

Ilkg

Input leakage current

VSS < VIN < VDD

±1

µA

Static current consumption

Floating input mode(4)(5)

400

RPU

Weak pull-up equivalent resistor(6)

VIN =VSS VDD = 5V

120

250



CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall time(1)

CL = 50pF

Between 10% and 90%

tr(IO)out

Output low to high level rise time(1)

tw(IT)in

External interrupt pulse time(7)

1tCPU

Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specification. A

positive injection is induced by VIN >VDD while a negative injection is induced by VIN <VSS. Refer to Section 19.2.2:

Current characteristics for more details.

Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested

in production. This value depends on VDD and temperature values.

The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the

particular ADC channel is selected (with port configured in input floating mode). When the ADON bit is OFF, static current

consumption may result. This can be avoided by keeping the input voltage of this pin close to VDD or VSS.

The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in

Figure 81).

To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

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