ST72325AR7-Auto datasheet(229/243 Pages) STMICROELECTRONICS

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ST72325xxx-Auto

Device configuration and ordering information

Doc ID 13770 Rev 3

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OPT5

CSS

Clock security system on/off

This option bit enables or disables the clock security system (CSS)

function which includes the clock filter and the backup safe oscillator.

0: CSS enabled

1: CSS disabled

OPT4:3

VD[1:0]

Voltage detection

These option bits enable the voltage detection block (LVD and AVD)

with a selected threshold for the LVD and AVD (EVD + AVD).

00: Selected LVD = Highest threshold (VDD~4V)

01: Selected LVD = Medium threshold (VDD~3.5V)

10: Selected LVD = Lowest threshold (VDD~3V)

11: LVD and AVD off

Caution: If the medium or low thresholds are selected, the detection

may occur outside the specified operating voltage range. Below 3.8V,

device operation is not guaranteed. For details on the AVD and LVD

threshold levels refer to Section 19.3.2: Operating conditions with low

voltage detector (LVD).

OPT2:1

Reserved, must be kept at default value

OPT0

FMP_R

Flash memory readout protection

Readout protection, when selected, provides a protection against

program memory content extraction and against write access to Flash

memory.

Erasing the option bytes when the FMP_R option is selected causes

the whole user memory to be erased first, after which the device can

be reprogrammed. Refer to Section 4.3.1: Readout protection and the

ST7 Flash Programming Reference Manual for more details.

0: Readout protection enabled

1: Readout protection disabled

Table 146.

Option byte 1 bit description

Bit

Name

Function

OPT7

PKG1

Package selection bit 1

This option bit selects the package (see Table 147: Package selection

(OPT7)).

OPT6

RSTC

RESET clock cycle selection

This option bit selects the number of CPU cycles applied during the

RESET phase and when exiting Halt mode. For resonator oscillators,

it is advised to select 4096 due to the long crystal stabilization time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

OPT5:4

OSCTYPE[1:0]

Oscillator type

These option bits select the ST7 main clock source type.

00: Clock source = Resonator oscillator

01: Reserved

10: Clock source = Internal RC oscillator

11: Clock source = External source

Table 145.

Option byte 0 bit description (continued)

Bit

Name

Function

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