ST72361AR4-Auto datasheet(133/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

8-bit timer (TIM8)

Doc ID 12468 Rev 3

133/279

Then, on a valid event on the ICAP1 pin, the counter is initialized to FCh and OLVL2 bit is

loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the

ICIE bit is set.

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two

steps:

Reading the SR register while the ICFi bit is set.

An access (read or write) to the ICiLR register.

The OC1R register value required for a specific timing application can be calculated using

the following formula:

Where:

Pulse period (in seconds)

fCPU

PLL output x2 clock frequency in hertz (or fOSC/2 if PLL is not enabled)

PRESC =

Timer prescaler factor (2, 4, 8 or 8000 depending on the CC[1:0] bits, see

Table 55)

When the value of the counter is equal to the value of the contents of the OC1R register, the

OLVL1 bit is output on the OCMP1 pin, (see Figure 68).

Note:

The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate

an Output Compare interrupt.

When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to

perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take

care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can

also generates interrupt if ICIE is set.

When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time has been elapsed but cannot generate an

output waveform because the level OLVL2 is dedicated to the one pulse mode.

event occurs

Counter

= OC1R

OCMP1 = OLVL1

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FCh

ICF1 bit is set

ICR1 = Counter

OCiR Value =

t * fCPU

PRESC

- 5

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