ST72361AR4-Auto datasheet(148/279 Pages) STMICROELECTRONICS

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Serial peripheral interface (SPI)

ST72361xx-Auto

148/279

Doc ID 12468 Rev 3

MISO pin and the MOSI pin are directly connected between the master and the slave

device.

Note:

If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

resetting the SPE bit.

Figure 74.

Data clock timing diagram

14.5

Error flags

14.5.1

Master mode fault (MODF)

Master mode fault occurs when the master device’s SS pin is pulled low.

When a Master mode fault occurs:

●

The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.

●

The SPE bit is reset. This blocks all output from the device and disables the SPI

peripheral.

●

The MSTR bit is reset, thus forcing the device into slave mode.

SCK

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

CPHA = 1

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MOSI

(to slave)

CAPTURE STROBE

CPHA = 0

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

(from slave)

(CPOL = 1)

SCK

(CPOL = 0)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

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