ST72361AR4-Auto datasheet(151/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

Serial peripheral interface (SPI)

Doc ID 12468 Rev 3

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Figure 76.

Single master / multiple slave configuration

14.6

Low power modes

Using the SPI to wake up the device from halt mode

In slave configuration, the SPI is able to wake up the device from HALT mode through a

SPIF interrupt. The data received is subsequently read from the SPIDR register when the

software is running (interrupt vector fetch). If multiple data transfers have been performed

before software clears the SPIF bit, then the OVR bit is set by hardware.

Note:

When waking up from HALT mode, if the SPI remains in Slave mode, it is recommended to

perform an extra communications cycle to bring the SPI from HALT mode state to normal

state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution:

The SPI can wake up the device from HALT mode only if the Slave Select signal (external

SS pin or the SSI bit in the SPICSR register) is low when the device enters HALT mode. So,

if Slave selection is configured as external (see Slave select management), make sure the

master drives a low level on the SS pin when the slave enters HALT mode.

MISO

MOSI

MISO

SCK

Slave

Device

Slave

Device

Slave

Device

Slave

Device

Master

Device

Table 56.

Effect of low power modes on SPI

Mode

Description

WAIT

No effect on SPI.

SPI interrupt events cause the device to exit from WAIT mode.

HALT

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI operation resumes when the device is

woken up by an interrupt with “exit from HALT mode” capability. The data

received is subsequently read from the SPIDR register when the software is

running (interrupt vector fetching). If several data are received before the wake-

up event, then an overrun error is generated. This error can be detected after

the fetch of the interrupt routine that woke up the Device.

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