STM32F383CC datasheet(14/125 Pages) STMICROELECTRONICS

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Functional overview

STM32F383xx

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DocID023367 Rev 2

3.7.2

Power supply supervisor

Device power on reset is controlled through the external NPOR pin. The device remains in

reset mode when NPOR is held low. NPOR pin has an internal pull-up resistor so the

external driver can be open drain type.

To guarantee a proper power-on reset, the NPOR pin must be held low until VDD is stable.

When VDD is stable, the reset state can be exited by:

•

either putting the NPOR pin in high impedance. NPOR pin has an internal pull up.

•

or forcing the pin to high level by connecting it to VDDA.

3.7.3

Low-power modes

The STM32F383xx supports two low-power modes to achieve the best compromise

between low power consumption, short startup time and available wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the USARTs, the I2Cs, the

CEC and the RTC alarm.

3.8

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and

the low speed APB (APB1) domains. The maximum frequency of the AHB and the high

speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed

APB domain is 36 MHz.

3.9

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

STM32F383CC Datasheet(PDF) 14 Page - STMicroelectronics

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