Theory of operation

STHVDAC-253M

12/27

DocID025735 Rev 1

3.10

Trigger Mode

To meet precise timing requirements and avoid RFFE interface traffic congestion at critical

timing, trigger mode has been implemented in the RFFE interface.

Two triggers (TRIG0 and TRIG1) are available and can be controlled through the RFFE

interface.

Registers 0 and 1 (DAC C and DAC B) are associated to TRIG0, and register 2 (DAC A) is

associated to TRIG1. Each trigger can be activated independently.

3.10.1

Trigger mode enabled:

The different triggers are enabled unsetting corresponding trigger mask bits in register 28.

In this case, once in ACTIVE mode, the following sequence must be followed to control the

HVDAC outputs:

Send any valid register 0/1/2 write command sequence. The new register values will be

temporarily stored in shadow registers.

Send a register28 write command sequence, setting trigger bits and keeping Trigger mask

bits low. The shadow registers will be loaded to destination registers and this will trigger the

corresponding DAC outputs to their new values (see Figure 5).

3.10.2

Trigger mode disabled (default mode):

The different triggers are disabled setting corresponding trigger mask bits in register 28.

In this case, any valid register write command sequence is directly loaded to the destination

register, directly triggering the corresponding DAC output to its new value.

The following logic diagram illustrates the trigger mode function. By default the trigger mode

is disable and the data are directly sent to the register in order to change the outputs without

Trigger.

Figure 5. Logic diagram trigger mode

SHADOW_REGISTER_B and C

OUTPUT_C

SHADOW_REGISTER_A

REGISTER_A

OUTPUT_A

TRIG_MASK_1

TRIG_1

TRIG_MASK_1

TRIG_0

TRIG_MASK_0

REGISTER_B and C

OUTPUT_B

TRIG_MASK_0

DATA_A

True data to register

True data to register

False data to shadow

False data to shadow

DATA_B

DATA_C