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AT89C51AC3-RDTIM Datasheet(PDF) 87 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM Datasheet(HTML) 87 Page - ATMEL Corporation |
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87 / 141 page  87 AT89C51AC3 4383A–8051–10/04 Figure 46. Data Transmission Format (CPHA = 0) Figure 47. Data Transmission Format (CPHA = 1) Figure 48. CPHA/SS Timing As shown in Figure 46, the first SCK edge is the MSB capture strobe. Therefore, the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each Byte transmitted (Figure 48). Figure 47 shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmis- sions (Figure 48). This format may be preferred in systems having only one Master and only one Slave driving the MISO data line. Queuing transmission For an SPI configured in master or slave mode, a queued data byte must be transmit- ted/received immediately after the previous transmission has completed. MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 MSB LSB 13 24 5 6 7 8 Capture Point SS (to Slave) MISO (from Slave) MOSI (from Master) SCK (CPOL = 1) SCK (CPOL = 0) SPEN (Internal) SCK Cycle Number MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 MSB LSB 13 2 4 567 8 Capture Point SS (to Slave) MISO (from Slave) MOSI (from Master) SCK (CPOL = 1) SCK (CPOL = 0) SPEN (Internal) SCK Cycle Number Byte 1 Byte 2 Byte 3 MISO/MOSI Master SS Slave SS (CPHA = 1) Slave SS (CPHA = 0) |
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