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AT89C51AC3-RDTIM Datasheet(PDF) 119 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM Datasheet(HTML) 119 Page - ATMEL Corporation |
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119 / 141 page  119 AT89C51AC3 4383A–8051–10/04 Table 70. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register 1 Reset Value = XXXX 0X0Xb 7654 3210 ---- SPIH - PADCH - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3SPIH SPI Interrupt Priority Level Most Significant bit SPIH SPIL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest 2- Reserved The value read from this bit is indeterminate. Do not set this bit. 1 PADCH ADC Interrupt Priority Level Most Significant bit PADCH PADCL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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