ADC31RF80IRMP datasheet(45/136 Pages) TI1

45 / 136 page

NCO

2949.12 MSPS

38230

1720.35 MHz

u S

NCO

DDCxNCOy

ADC31RF80

www.ti.com

SBAS860 – AUGUST 2017

Product Folder Links: ADC31RF80

Submit Documentation Feedback

8.3.4.3.12

Latency With Decimation Options

Table 4 describes device latency for different DDC options. At higher decimation options, latency increases

because of the increase in number of taps in the decimation filter.

Table 4. Latency With Different Decimation Options

DECIMATION OPTION

TOTAL LATENCY, DEVICE CLOCK CYCLES

Divide-by-4

516

Divide-by-6

746

Divide-by-8

621

Divide-by-9

763.5

Divide-by-10

811

Divide-by-12

897

Divide-by-16

1045

Divide-by-18

1164

Divide-by-20

1256

Divide-by-24

1443

Divide-by-32

1773

8.3.4.4 Numerically-Controlled Oscillators (NCOs) and Mixers

The ADC31RF80 is equipped with three independent, complex NCOs. Equation 2 shows how the oscillator

generates a complex exponential sequence.

x[n] = e

–jωn

where

•

frequency (ω) is specified as a signed number by the 16-bit register setting

(2)

The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down

to 0 Hz.

The ADC has two DDCs. The first DDC has three NCOs and the second DDC has one NCO. The first DDC can

dynamically select one of the three NCOs based on the GPIO pin or SPI selection. In wide-bandwidth mode

(lower decimation factors, for example, 4 and 6), there can only be one active DDC. The NCO frequencies can

be programmed independently through the DDCx, NCO[4:1], and the MSB and LSB register settings.

Equation 3 gives the NCO frequency setting that is set by the 16-bit register:

where

•

x = 0, 1

•

y = 1 to 4

(3)

For example:

If fS = 2949.12 MSPS, then the NCO register setting = 38230 (decimal).

Thus, Equation 4 defines fNCO:

(4)

Any register setting changes that occur after the JESD204B interface is operational results in a non-deterministic

NCO phase. If a deterministic phase is required, the JESD204B interface must be reinitialized after changing the

8.3.5 NCO Switching

The first DDC (DDC0) provides three different NCOs that can be used for phase-coherent frequency hopping.

This feature is available in both single-band and dual-band mode, but only affects DDC0.

ADC31RF80IRMP Datasheet(PDF) 45 Page - Texas Instruments

ADC31RF80IRMP Datasheet(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL