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ADC31RF80IRMP Datasheet(PDF) 63 Page - Texas Instruments |
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ADC31RF80IRMP Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 136 page  tSDOUT SCLK SDOUT 63 ADC31RF80 www.ti.com SBAS860 – AUGUST 2017 Product Folder Links: ADC31RF80 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table 25. SPI Input Description SPI BIT DESCRIPTION OPTIONS R/W bit Read/write bit 0 = SPI write 1 = SPI read back M bit SPI bank access 0 = Analog SPI bank (master) 1 = All digital SPI banks (main digital, interleaving, decimation filter, JESD digital, and so forth) P bit JESD page selection bit 0 = Page access 1 = Register access CH bit SPI access for a specific channel of the JESD SPI bank. Useful for the dual-channel device, ADC32RF80. — ADDR[11:0] SPI address bits — DATA[7:0] SPI data bits — Figure 135 shows the SDOUT timing when data are read back from a register. Data are placed on the SDOUT bus at the SCLK falling edge after a delay of tSDOUT (10 ns typical) so that the data can be latched at the SCLK rising edge by the external receiver. Figure 135. SDOUT Timing |
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