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ADC31RF80IRMP Datasheet(PDF) 71 Page - Texas Instruments

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Part # ADC31RF80IRMP
Description  3-GSPS Telecom Receiver and Feedback Device
PDF  136 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC31RF80IRMP Datasheet(HTML) 71 Page - Texas Instruments

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ADC31RF80
www.ti.com
SBAS860 – AUGUST 2017
71
Product Folder Links: ADC31RF80
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Register Maps (continued)
Table 26. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
Main Digital Page (680000h, M = 1)
000
0
0
0
0
0
0
0
DIG CORE RESET
GBL
0A2
0
0
0
0
NQ ZONE EN
NYQUIST ZONE
0A5
Sampling Frequency
0A9
0
0
0
0
Sampling
Frequency Enable
0
1
1
0B0
Band1 Lower-Edge Frequency LSB Setting
0B1
0
0
0
Band1 Lower-Edge Frequency MSB Setting
0B2
Band1 Upper-Edge Frequency LSB Setting
0B3
0
0
Band1 Frequency
Range Enable
Band1 Upper-Edge Frequency MSB Setting
0B4
Band2 Lower-Edge Frequency LSB Setting
0B5
0
0
0
Band2 Lower-Edge Frequency MSB Setting
0B6
Band2 Upper-Edge Frequency LSB Setting
0B7
0
0
Band2 Frequency
Range Enable
Band2 Upper-Edge Frequency MSB Setting
0B8
Band3 Lower-Edge Frequency LSB Setting
0B9
0
0
0
Band3 Lower-Edge Frequency MSB Setting
0BA
Band3 Upper-Edge Frequency LSB Setting
0BB
0
0
Band3 Frequency
Range Enable
Band3 Upper-Edge Frequency MSB Setting
JESD DIGITAL PAGE (690000h, M = 1)
001
CTRL K
0
0
TESTMODE EN
0
LANE ALIGN
FRAME ALIGN
TX LINK DIS
002
SYNC REG
SYNC REG EN
0
0
12BIT MODE
JESD MODE0
003
LINK LAYER TESTMODE
LINK LAY RPAT
LMFC MASK
RESET
JESD MODE1
JESD MODE2
RAMP 12BIT
004
0
0
0
0
0
0
REL ILA SEQ
006
SCRAMBLE EN
0
0
0
0
0
0
0
007
0
0
0
FRAMES PER MULTIFRAME (K)
016
0
40X MODE
0
0
0
0
017
0
0
0
0
LANE0
POL
LANE1
POL
LANE2
POL
LANE3
POL



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