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BLUENRG-2 Datasheet(PDF) 67 Page - STMicroelectronics |
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BLUENRG-2 Datasheet(HTML) 67 Page - STMicroelectronics |
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67 / 190 page  BlueNRG-2 Functional details DocID030675 Rev 2 67/190 Bit Field name Reset RW Description 3 TXMIS 0x0 R Transmit Masked Interrupt Status: gives the interrupt status after masking of the transmit interrupt. 4 TURMIS 0x0 R Transmit Underrun Masked Interrupt Status: gives the interrupt status after masking of the transmit underrun interrupt. 5 TEMIS 0x0 R Transmit FIFO Empty Masked Interrupt Status: gives the interrupt status after masking of the transmit FIFO empty interrupt. 31:6 RESERVED 0x0 R RESERVED Table 64: SPI - ICR register description: address offset SPI_BASE_ADDR+0x20 Bit Field name Reset RW Description 0 RORIC 0x0 W Receive Overrun Clear Interrupt: writing 1 clears the receive overrun interrupt. 1 RTIC 0x0 W Receive Time Out Clear Interrupt: writing 1 clears the receive timeout interrupt. 2 TURIC 0x0 W Transmit Underrun Clear Interrupt: writing 1 clears the transmit overrun interrupt. 31:3 RESERVED 0x0 R RESERVED Table 65: SPI - DMACR register description: address offset SPI_BASE_ADDR+0x24 Bit Field name Reset RW Description 0 RXDMASE 0x0 RW Single receive DMA request. 0: Single transfer DMA in receive disable. 1: Single transfer DMA in receive enable. 1 RESERVED 0x0 R RESERVED 2 TXDMASE 0x0 RW Single transmit DMA request. 0: Single transfer DMA in transmit disable. 1: Single transfer DMA in transmit enable. 31:3 RESERVED 0x0 R RESERVED Table 66: SPI – RXFRM register description: address offset SPI_BASE_ADDR+0x28 Bit Field name Reset RW Description 31:0 RXFRM 0x00000000 RW SPI Receive Frame register. Indicates the number of frames to receive from the slave. Table 67: SPI – CHN register description: address offset SPI_BASE_ADDR+0x2C Bit Field name Reset RW Description 31:0 CHN 0x00000000 RW Dummy character register. |
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