BLUENRG-2 datasheet(68/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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Table 68: SPI

– WDTXF register description: address offset SPI_BASE_ADDR + 0x30

Bit

Field

name

Reset

Description

31:0

RXFRM

0x00000000

SPI transmit FIFO receive frame number. Indicates the

number of frames to receive from the TX FIFO.

Table 69: SPI - ITCR register description: address offset SPI_BASE_ADDR+0x80

Bit

Field name

Reset

Description

RESERVED

0x0

RESERVED

SWAPFIFO

0x0

FIFO control mode:

0: FIFO normal mode. Write in TDR register puts data in TX

FIFO and read from TDR register read data from RX FIFO.

1: FIFO swapped mode. Write in TDR register puts data in RX

FIFO and read from TDR register read data from TX FIFO.

The registers SWAPFIFO and TDR allow to clear the TX FIFO

from unwanted data

31:2

RESERVED

0x0

RESERVED

Table 70: SPI

– TDR register description: address offset SPI_BASE_ADDR+0x8C

Bit

Field

name

Reset

Description

31:0

TDR

0x00000000

Allows reading out data from TX FIFO if the SWAPFIFO

bitfield is set.

The registers SWAPFIFO and TDR allow to clear the TX

FIFO from unwanted data

3.9

UART

3.9.1

Introduction

The BlueNRG-2 integrates a universal asynchronous receiver/transmitter that support

much of the functionality of the industry-standard 16C650 UART.

Main features are:



Programmable baud rates up to 2 Mbps.



Programmable data frame of 5, 6, 7 or 8 bits of data.



Even, odd, stick or no-parity bit generation and detection.



Programmable 1 or 2 stop bit.



Support of hardware flow control using CTS and RTS pins.



Support of software flow control using programmable Xon/Xoff characters



False start bit detection.



Line break generation and detection.



Programmable 8-bit wide, 64-deep transmit FIFO and 12-bit wide (8-bit data and 4-bit

status), 64-deep receive FIFO.



Support for Direct Memory Access (DMA).

3.9.2

Functional description

The UART performs serial-to-parallel conversion on data asynchronously received from a

peripheral device on the UART_RX pin, and parallel-to-serial conversion on data written by

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