BLUENRG-2 datasheet(81/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

81/190

Bit

Field name

Reset

Description

SPS_RX

0x0

RX stick parity select:

0: stick parity is disabled.

1: when PEN_RX = 1b (parity enabled) and EPS_RX = 1b

(even parity), the parity is checked as a 0. When PEN_RX = 1b

and EPS_RX = 0b (odd parity), the parity bit is checked as a 1.

31:8

RESERVED

0x0

RESERVED

Table 83: UART - IBRD register description: address offset UART_BASE_ADDR+0x24

Bit

Field name

Reset

Description

15:0

DIVINT

0x0

Baud rate integer. The baud rate divisor is calculated as

follows:

When OVSFACT = 0b in the CR register: Baud rate divisor =

(Frequency (UARTCLK)/(16*Baud rate))

When OVSFACT = 1b in CR register: Baud rate divisor =

(Frequency (UARTCLK)/(8*Baud rate))

where frequency (UARTCLK) is the UART reference clock

frequency. The baud rate divisor comprises the integer value

(DIVINT) and the fractional value (DIVFRAC). The contents of

the IBRD and FBRD registers are not updated until

transmission or reception of the current character has

completed.

31:16

RESERVED

0x0

RESERVED

Table 84: UART - FBRD register description: address offset UART_BASE_ADDR+0x28

Bit

Field name

Reset

Description

5:0

DIVFRAC

0x0

Baud rate fraction. Baud rate integer. The baud rate divisor is

calculated as follows:

When OVSFACT = 0b in the CR register: Baud rate divisor =

(Frequency (UARTCLK)/(16*Baud rate))

When OVSFACT = 1b in CR register: Baud rate divisor =

(Frequency (UARTCLK)/(8*Baud rate))

where Frequency (UARTCLK) is the UART reference clock

frequency. The baud rate divisor comprises the integer value

(DIVINT) and the fractional value (DIVFRAC). The contents of

the IBRD and FBRD registers are not updated until

transmission or reception of the current character has

completed.

31:6

RESERVED

0x0

RESERVED

Table 85: UART - LCRH_TX register description: address offset UART_BASE_ADDR+0x2C

Bit

Field name

Reset

Description

BRK

0x0

Send break. This bit allows a continuous low-level to be forced

on TX output, after completion of the current character. This bit

must be asserted for at least one complete frame transmission

time in order to generate a break condition. The transmit FIFO

contents remain unaffected during a break condition.

0: Normal transmission.

1: Break condition transmission.

BLUENRG-2 Datasheet(PDF) 81 Page - STMicroelectronics

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