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BLUENRG-2 Datasheet(PDF) 161 Page - STMicroelectronics |
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BLUENRG-2 Datasheet(HTML) 161 Page - STMicroelectronics |
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161 / 190 page  BlueNRG-2 Memory mapping DocID030675 Rev 2 161/190 5 Memory mapping Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and highest numbered byte the most significant. The addressable memory space is divided into 16 main blocks, each 256 MB. All the memory areas that are not allocated to on-chip memories and peripherals are considered “RESERVED”. For the detailed mapping of an available memory and register areas, please refer to the memory map in table below and to the register lists detailed in each of the peripheral sections. Table 211: Memory mapping Address Cortex-M0 address map Size Description 0x0000_0000 – 0x0000_0FFF Code 4 kB ROM 0x1000_0000 – 0x1000_0FFF Code 4 kB ROM 0x1004_0000 – 0x1006_7FFF Code 256 kB Flash 0x2000_0000 – 0x2000_2FFF SRAM0 always on 12 kB SRAM 0x2000_3000 – 0x2000_5FFF SRAM1 switchable 12 kB SRAM 0x2000_6000 – 0x3FFF_FFFF RESERVED 0x4000_0000 APB peripheral 4 kB GPIO 0x4010_0000 4 kB Flash controller 0x4020_0000 4 kB System controller 0x4030_0000 4 kB UART 0x4040_0000 4 kB SPI 0x4050_0000 4 kB RESERVED 0x4060_0000 4 kB RESERVED 0x4070_0000 4 kB Watchdog 0x4080_0000 4 kB ADC 0x4090_0000 4 kB Clock generator 0x40A0_0000 4 kB I2C2 0x40B0_0000 4 kB I2C1(1) 0x40C0_0000 4 kB AHB up converter 0x40D0_0000 4 kB MFT1 0x40E0_0000 4 kB MFT2 0x40F0_0000 4 kB RTC 0x4100_0000 4 kB RESERVED 0x4800_0000 4 kB BLE controller 0x4810_0000 4 kB BLE clock generator |
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