AL2100-DS00-R datasheet(25/52 Pages) BOARDCOM

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Preliminary Data Sheet

AL2100

11/11/02

Broa d c om Co rp o r a ti o n

Document

AL2100-DS01-405-R

100base-Tx PHY Registers

Page 17

CONTROL REGISTER

STATUS REGISTER

Table 6: Register 0: Control Register Bit Description

Bit

Name

Description

Mode

Default

Reset

1 = PHY reset.

This bit is self-clearing.

RW/SC

Loop back

1 = Enable loopback mode. This loops back TXD to RXD, and

ignores all activity on the cable media.

0 = Normal operation.

Speed Select

Set to 1 for normal operation; 0 is prohibited.

ANEN Enable

1 = Enable auto-negotiation process (overrides 0.13 and 0.8)

0 = Disable auto-negotiation process. Mode selection is controlled

via bit 0.8, 0.13 or through the mode pins.

Set by ANEN

Power Down

1 = Power-down all blocks. While in the power-down state, the PHY

responds to management transactions. Setting PDOWN, pin

24, to low has the same result.

0 = Normal operation.

Isolate

1 = Electrically isolate the PHY from MII. PHY still responds to SMI.

0 = Normal operation.

Restart ANEN

1 = Restart auto-negotiation process.

0 = Normal operation.

RW/SC

Duplex Mode

1 = Full duplex.

0 = Half duplex.

Set by a mode pin

Collision Test

1 = Enable collision test, which issues the COL signal in response

to the assertion of the TX_EN signal. Collision test is disabled

when the PCSBP pin is high. Collision test is enabled

regardless of the duplex mode.

0 = Disable COL test.

6:0

Reserved

0000000

Table 7: Register 1: Status Register Bit Description

Bit

Name

Description

Mode

Default

100Base-T4

Permanently tied to 0 indicates no 100BaseT4 capability.

100Base-TX Full

Duplex

1 = 100BaseTX full-duplex capable.

0 = Not 100BaseTX full-duplex capable.

set by DUPLEX pin

100Base-TX Half

Duplex

1 = 100BaseTX half-duplex capable.

0 = Not TX half-duplex capable.

set by DUPLEX pin

10Base-T Full

Duplex

1 = 10BaseT full-duplex capable.

0 = Not 10BaseT-full duplex capable.

10Base-T Half

Duplex

1 = 10BaseT half-duplex capable.

0 = Not 10BaseT half-duplex capable.

10:7

Reserved

0000

MF Preamble

Suppression

The PHY is able to perform management transactions

without an MDIO preamble. The management interface

needs a minimum of 32 bits of preamble after reset.

AL2100-DS00-R Datasheet(PDF) 25 Page - Broadcom Corporation.

AL2100-DS00-R Datasheet(HTML) 25 Page - Broadcom Corporation.

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