AL2100-DS00-R datasheet(20/52 Pages) BOARDCOM

20 / 52 page

AL2100

Preliminary Data Sheet

11/11/02

Broa d c om Co rp o r a ti o n

Page 12

100Base-Twisted Pair PHY

Document

AL2100-DS01-405-R

ANALOG ADAPTIVE EQUALIZER

The analog adaptive equalizer removes inter-symbol interference (ISI) created by the transmission channel media. The PHY

is designed to accommodate a maximum of 140 meters UTP CAT-5 cable. An AT&T 1061 CAT-5 cable of this length typically

has an attenuation of 31dB at 100 MHz. A typical attenuation of 100-meter cable is 21dB. The worst case cable attenuation

is around 24-26dB, as defined by TP-PMD specification. The amplitude and phase distortion from the cable cause ISI, which

makes clock and data recovery difficult. The adaptive equalizer is designed to closely match the inverse transfer function of

the twisted-pair cable. The equalizer has the ability to change its equalizer frequency response according to cable length.

The equalizer tunes itself automatically for any cable, compensating for the amplitude and phase distortion introduced by

the cable.

CLOCK RECOVERY

The equalized MLT-3 signal passes through the slicer circuit, and gets converted to NRZI format. The PHY uses a

proprietary mixed-signal phase locked loop (PLL) to extract clock information from the incoming NRZI data. The extracted

clock is used to retime the data stream, and set the data boundaries. The transmit clock is locked to the 25 MHz clock input,

while the receive clock is locked to the incoming data streams. When initial lock is achieved, the PLL switches to the data

stream, extracts the 125 MHz clock, and uses it for bit framing for the recovered data. The recovered 125 MHz clock is also

used to generate the 25 MHz RX_CLK signal. The PLL requires no external components for its operation, and has high noise

immunity and low jitter. It provides fast phase alignment, and locks to data in one transition. Its data/clock acquisition time

after power-on is less than 60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of

signal transitions. When no valid data is present, i.e. when the SD is de-asserted, the PLL switches and locks onto TX_CLK.

This provides a continuously running RX_CLK. At the PCS interface, the 5-bit data RXD[4:0] is synchronized to the 25 MHz

RX_CLK.

Table 4: SPD100 0 Settings

Name

Description

Speed Select

1 = 100Mbps

Set to 1 for normal operation. 0 is prohibited.

ANEN Enable

1 = Enable auto-negotiation

0 = Disable auto-negotiation

Duplex

The default value is !ANEN && DUPLEX

100Base-TX Full Duplex

The default value of this bit is DUPLEX

100Base-TX

The default value of this bit is ANEN ||!DUPLEX

AL2100-DS00-R Datasheet(PDF) 20 Page - Broadcom Corporation.

AL2100-DS00-R Datasheet(HTML) 20 Page - Broadcom Corporation.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL