ISL8201M

FN6657 Rev 3.00

Page 10 of 16

October 28, 2014

final expected voltage (at close to 100% duty cycle, with

in-rush current charging the output capacitors (only the

is not acceptable, then consider changing the sequencing of

the power supplies, sharing the same supply, or adding

sequencing logic to the COMP/EN pin to delay the soft-start

Considerations” on page 11).

If ISL8201M is disabled after soft-start (by pulling COMP/EN

pin low), and afterwards enabled (by releasing the COMP/EN

pin), then the full initialization (including OCP sample) will take

place. However, there is no new OCP sampling during

overcurrent retries. If the output is shorted to GND during soft-

start, the OCP will handle it, as described in the next section.

Overcurrent Protection (OCP)

The overcurrent function protects the converter from a shorted

overcurrent trip level.

This method enhances the converter's efficiency and reduces

cost by eliminating a current sensing resistor. If overcurrent is

detected, the output immediately shuts off. It cycles the soft-

start function in a hiccup mode (2 dummy soft-start time-outs,

then up to one real one) to provide fault protection. If the

shorted condition is not removed, this cycle will continue

indefinitely.

Following POR (and 6.8ms delay), the ISL8201M initiates the

overcurrent protection sample and hold operation. The low-

side gate driver is disabled to allow an internal 21.5µA current

samples this voltage (which is referenced to the PGND pin) at

the ISET pin, and holds it in a counter and DAC combination.

This sampled voltage is held internally as the overcurrent set

point, for as long as power is applied, or until a new sample is

taken after coming out of a shut-down.

The actual monitoring of the low-side MOSFET ON-resistance

starts 200ns (nominal) after the edge of the internal PWM logic

signal (that creates the rising external low-side gate signal).

This is done to allow the gate transition noise and ringing on

the PHASE pin to settle out before monitoring. The monitoring

ends when the internal PWM edge (and thus low-side gate

signal) goes low. The OCP can be detected anywhere within

the above window.

If the converter is running at high duty cycles around 75% for

600kHz operation, then the low-side gate pulse width may not

For those cases, if the low-side gate signal is too narrow (or

not there at all) for 3 consecutive pulses, then the third pulse

will be stretched and/or inserted to the 425ns minimum width.

This allows for OCP monitoring every third pulse under this

condition. This can introduce a small pulse-width error on the

output voltage, which will be corrected on the next pulse; and

the output ripple voltage will have an unusual 3-clock pattern,

which may look like jitter.

The overcurrent function will trip at a peak inductor current

where:

and 9m

Note: ISL8201M has integrated 3.57k

in Equation 3:

The scale factor of 2 doubles the trip point of the MOSFET

OC trip point varies in a system mainly due to the MOSFET

To avoid overcurrent tripping in the normal operating load

to 3:

on page 3.

FIGURE 18. PRE-BIASED START-UP - OVERCHARGED

500mV/DIV







--------------------------------------------

=

(EQ. 2)



+

-------------------------------------------------------

=

(EQ. 3)