ISL6566 datasheet(17/30 Pages) RENESAS

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ISL6566

FN9178 Rev 4.00

Page 17 of 30

Mar 9, 2006

Advanced Adaptive Zero Shoot-Through Deadtime

Control (Patent Pending)

The integrated drivers incorporate a unique adaptive deadtime

control technique to minimize deadtime, resulting in high

efficiency from the reduced freewheeling time of the lower

MOSFET body-diode conduction, and to prevent the upper and

lower MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.3V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is released

to rise. An auto-zero comparator is used to correct the rDS(ON)

drop in the phase voltage preventing false detection of the

-0.3V phase level during rDS(ON conduction period. In the case

of zero current, the UGATE is released after 35ns delay of the

LGATE dropping below 0.5V. During the phase detection, the

disturbance of LGATE falling transition on the PHASE node is

blanked out to prevent falsely tripping. Once the PHASE is

high, the advanced adaptive shoot-through circuitry monitors

the PHASE and UGATE voltages during a PWM falling edge

and the subsequent UGATE turn-off. If either the UGATE falls

to less than 1.75V above the PHASE or the PHASE falls to less

than +0.8V, the LGATE is released to turn on.

Internal Bootstrap Device

All three integrated drivers feature an internal bootstrap

schottky diode. Simply adding an external capacitor across

the BOOT and PHASE pins completes the bootstrap circuit.

The bootstrap function is also designed to prevent the

bootstrap capacitor from overcharging due to the large

negative swing at the PHASE node. This reduces voltage

stress on the boot to phase pins.

The bootstrap capacitor must have a maximum voltage

rating above PVCC + 5V and its capacitance value can be

chosen from the following equation:

where QG1 is the amount of gate charge per upper MOSFET

at VGS1 gate-source voltage and NQ1 is the number of

control MOSFETs. The

VBOOT_CAP term is defined as the

allowable droop in the rail of the upper gate drive.

Gate Drive Voltage Versatility

The ISL6566 provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The controller

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously.

Initialization

Prior to initialization, proper conditions must exist on the

ENLL, VCC, PVCC and the VID pins. When the conditions are

met, the controller begins soft-start. Once the output voltage is

within the proper window of operation, the controller asserts

PGOOD.

Enable and Disable

While in shutdown mode, the PWM outputs are held in a

high-impedance state. This forces the drivers to short gate-

to-source of the upper and lower MOSFET’s to assure the

MOSFETs remain off. The following input conditions must be

met before the ISL6566 is released from this shutdown

mode.

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this

threshold is reached, proper operation of all aspects of

the ISL6566 is guaranteed. Hysteresis between the rising

and falling thresholds assure that once enabled, the

ISL6566 will not inadvertently turn off unless the bias

voltage drops substantially (see Electrical

Specifications

CBOOT_CAP

QGATE

V

BOOT_CAP

--------------------------------------



QGATE

QG1 PVCC



VGS1

------------------------------------ NQ1



(EQ. 12)

50nC

20nC

FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

VBOOT_CAP (V)

1.6

1.4

1.2

0.8

0.6

0.4

0.2

0.0

0.3

0.0

0.1

0.2

0.4

0.5

0.6

0.9

0.7

0.8

1.0

QGATE = 100nC

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