ISL6566 datasheet(19/30 Pages) RENESAS

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ISL6566

FN9178 Rev 4.00

Page 19 of 30

Mar 9, 2006

Fault Monitoring and Protection

The ISL6566 actively monitors output voltage and current to

detect fault conditions. Fault monitors trigger protective

measures to prevent damage to a microprocessor load. One

common power good indicator is provided for linking to

external system monitors. The schematic in Figure 13

outlines the interaction between the fault monitors and the

power good signal.

Power Good Signal

The power good pin (PGOOD) is an open-drain logic output

that transitions high when the converter is operating after

soft-start. PGOOD pulls low during shutdown and releases

high after a successful soft-start. PGOOD transitions low

when an undervoltage, overvoltage, or overcurrent condition

is detected or when the controller is disabled by a reset from

ENLL, POR, or one of the no-CPU VID codes. If after an

undervoltage or overvoltage event occurs the output returns

to within under and overvoltage limits, PGOOD will return

high.

Undervoltage Detection

The undervoltage threshold is set at 82% of the VID code.

When the output voltage (VSEN-RGND) is below the

undervoltage threshold, PGOOD gets pulled low. No other

action is taken by the controller. PGOOD will return high if

the output voltage rises above 85% of the VID code.

Overvoltage Protection

The ISL6566 constantly monitors the difference between the

VSEN and RGND voltages to detect if an overvoltage event

occurs. During soft-start, while the DAC is ramping up, the

overvoltage trip level is the higher of DAC plus 150mV or a

fixed voltage, VOVP. The fixed voltage, VOVP, is 1.67V when

running in AMD Hammer, or VRM10 modes, and 1.97V for

VRM9 mode. Upon successful soft-start, the overvoltage trip

level is only DAC plus 150mV. OVP releases 50mV below its

trip point if it was “DAC plus 150mV” that tripped it, and

releases 100mV below its trip point if it was the fixed voltage,

VOVP, that tripped it. Actions are taken by the ISL6566 to

protect the microprocessor load when an overvoltage

condition occurs, until the output voltage falls back within set

limits.

At the inception of an overvoltage event, all LGATE signals

are commanded high, and the PGOOD signal is driven low.

This causes the controller to turn on the lower MOSFETs

and pull the output voltage below a level that might cause

damage to the load. The LGATE outputs remain high until

VDIFF falls to within the overvoltage limits explained above.

The ISL6566 will continue to protect the load in this fashion

as long as the overvoltage condition recurs.

Once an overvoltage condition ends the ISL6566 continues

normal operation and PGOOD returns high.

Pre-POR Overvoltage Protection

Prior to PVCC and VCC exceeding their POR levels, the

ISL6566 is designed to protect the load from any overvoltage

events that may occur. This is accomplished by means of an

internal 10k

 resistor tied from PHASE to LGATE, which

turns on the lower MOSFET to control the output voltage

until the overvoltage event ceases or the input power supply

cuts off. For complete protection, the low side MOSFET

should have a gate threshold well below the maximum

voltage rating of the load/microprocessor.

In the event that during normal operation the PVCC or VCC

voltage falls back below the POR threshold, the pre-POR

overvoltage protection circuitry reactivates to protect from

any more pre-POR overvoltage events.

Open Sense Line Protection

In the case that either of the remote sense lines, VSEN or

GND, become open, the ISL6566 is designed to detect this

and shut down the controller. This event is detected by

monitoring the voltage on the IREF pin, which is a local

version of VOUT sensed at the outputs of the inductors.

FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY

VID + 150mV

VSEN

0.82 x DAC

PGOOD

SOFT-START, FAULT

AND CONTROL LOGIC

ISEN

IREF

ISUM

ICOMP

OCSET

ROCSET

VDROOP

VOCSET +

VOVP

100uA

ISL6566 INTERNAL CIRCUITRY

RGND

+1V

VDIFF

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