ISL6566 datasheet(24/30 Pages) RENESAS

24 / 30 page

ISL6566

FN9178 Rev 4.00

Page 24 of 30

Mar 9, 2006

Fortunately, there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator, by compensating the L-C poles

and the ESR zero of the voltage mode approximation, yields a

solution that is always stable with very close to ideal transient

performance.

Select a target bandwidth for the compensated system, f0. The

target bandwidth must be large enough to assure adequate

transient performance, but smaller than 1/3 of the per-channel

switching frequency. The values of the compensation

components depend on the relationships of f0 to the L-C pole

frequency and the ESR zero frequency. For each of the

following three, there is a separate set of equations for the

compensation components.

In Equations 29, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent series resistance of

the bulk output filter capacitance; and VPP is the peak-to-peak

sawtooth signal amplitude as described in the Electrical

Specifications

Once selected, the compensation values in Equations 29

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

improved by making adjustments to RC. Slowly increase the

value of RC while observing the transient performance on an

oscilloscope until no further improvement is noted. Normally,

CC will not need adjustment. Keep the value of CC from

Equations 29 unless some performance issue is noted.

The optional capacitor C2, is sometimes needed to bypass

noise away from the PWM comparator (see Figure 20). Keep a

position available for C2, and be prepared to install a high-

frequency capacitor of between 22pF and 150pF in case any

leading edge jitter problem is noted.

Output Filter Design

The output inductors and the output capacitor bank together to

form a low-pass filter responsible for smoothing the pulsating

voltage at the phase nodes. The output filter also must provide

the transient energy until the regulator can respond. Because it

has a low bandwidth compared to the switching frequency, the

output filter limits the system transient response. The output

capacitors must supply or sink load current while the current in

the output inductors increases or decreases to meet the

demand.

In high-speed converters, the output capacitor bank is usually

the most costly (and often the largest) part of the circuit. Output

filter design begins with minimizing the cost of this part of the

circuit. The critical load parameters in choosing the output

capacitors are the maximum size of the load step,

I, the load-

current slew rate, di/dt, and the maximum allowable output-

voltage deviation under transient loading,

VMAX. Capacitors

are characterized according to their capacitance, ESR, and

ESL (equivalent series inductance).

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will initially

deviate by an amount approximated by the voltage drop across

the ESL. As the load current increases, the voltage drop across

the ESR increases linearly until the load current reaches its final

value. The capacitors selected must have sufficiently low ESL

and ESR so that the total output-voltage deviation is less than

the allowable maximum. Neglecting the contribution of inductor

current and regulator response, the output voltage initially

deviates by an amount

The filter capacitor must have sufficiently low ESL and ESR so

that

V < VMAX.

Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination with

bulk capacitors having high capacitance but limited high-

frequency performance. Minimizing the ESL of the high-

frequency capacitors allows them to support the output voltage

as the current increases. Minimizing the ESR of the bulk

capacitors allows them to supply the increased current with less

output voltage deviation.

The ESR of the bulk capacitors also creates the majority of the

output-voltage ripple. As the bulk capacitors sink and source

the inductor ac ripple current (see Interleaving and Equation 2),

a voltage develops across the bulk capacitor ESR equal to

IC,PP(ESR). Thus, once the output capacitors are selected, the

maximum allowable ripple voltage, VPP(MAX), determines the

lower limit on the inductance.

 LC

------------------- f0

RFB

f

0Vpp LC

0.66VIN

------------------------------------

0.66VIN

V

PPRFBf0

------------------------------------

Case 1:

 LC

------------------- f0

C ESR



------------------------------



RFB

VPP 2

2 f

2 LC

0.66 VIN

--------------------------------------------

0.66VIN



2 f

2 V

PPRFB LC

-------------------------------------------------------------

Case 2:

(EQ. 29)

C ESR



------------------------------

RFB

 f

0VppL

0.66 VIN ESR



------------------------------------------

0.66VIN ESR

 C

V

PPRFBf0 L

-------------------------------------------------

Case 3:

V

ESL

 di

-----

ESR

 I



(EQ. 30)

ESR



VIN NVOUT

–



 V

OUT

fSVINVPP MAX



------------------------------------------------------------



(EQ. 31)

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