WM9714CLGEFLSLASHRV datasheet(65/120 Pages) CIRRUS

65 / 120 page

WM9714L

Rev 4.0

AUXADC POWER MANAGEMENT

To save power, the AUXADC can be independently disabled when not used.

The AUXADC is powered-down using PADCPD, register 3Ch bit 15.

The state of the ADC is controlled using the bits described in Table 46.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3Ch

PADCPD

1 = off

AUXADC Disable Control

1 = Disabled

0 = Enabled

78h

15:14

PRP

Additional Enable for AUXADC

00 = Disabled

01 = Reserved

10 = Reserved

11 = Enabled

Table 46 AUXADC Power Management

INITIATION OF MEASUREMENTS

The WM9714L AUXADC interface supports both polling routines and DMA (direct memory access) to

control the flow of data from the AUX ADC to the host CPU.

In a polling routine, the CPU starts each measurement individually by writing to the POLL bit (register

74h, bit 9). This bit automatically resets itself when the measurement is completed.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

74h

POLL

Poll Measurement Control

Writing “1” initiates a measurement (when

CTC=0)

CTC

AUXADC Measurement Mode

0 = Polling mode

1 = Continuous mode (for DMA)

76h

9:8

Continuous Mode Conversion Rate

Continuous mode rate (DEL

≠ 1111)

00: 93.75 Hz (every 512 AC-Link frames)

01: 120 Hz (every 400 AC-Link frames)

10: 153.75 Hz (every 312 AC-Link frames)

11: 187.5Hz (every 256 AC-Link frames)

Continuous mode “fast rate” (DEL = 1111)

00: 8 kHz (every six AC-Link frames)

01: 12 kHz (every four AC-Link frames)

10: 24 kHz (every other AC-Link frame)

11: 48 kHz (every AC-Link frame)

Table 47 AUX ADC Control (Initiation of Measurements)

In continuous mode (CTC = 1), the WM9714L autonomously initiates measurements (or sets of

measurements) at the rate set by CR, and supplies the measured data to the CPU on one of the

unused AC’97 time slots. DMA-enabled CPUs can write the data directly into a FIFO without any

intervention by the CPU core. This reduces CPU loading and speeds up the execution of user

programs in handheld systems.

Note that the measurement frequency in continuous mode is also affected by the DEL bits (see

“Register Bits by Address”, Register 76h). The faster rates achieved when DEL = 1111 may be useful

when the ADC is used for multiple measurements.

WM9714CLGEFL/RV Datasheet(PDF) 65 Page - Cirrus Logic

WM9714CLGEFL/RV Datasheet(HTML) 65 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL